MT8920B
ST-BUS Parallel Access Circuit
Data Sheet
Features
•
•
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•
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High speed parallel access to the serial
ST-BUS
Parallel bus optimized for 68000
µP
(mode 1)
Fast dual-port RAM access (mode 2)
Access time: 120 nsec
Parallel bus controller (mode 3) - no external
controller required
Flexible interrupt capabilities - two
independent/programmable interrupt sources
with auto-vectoring
Selectable 24 and 32 channel operation
Programmable loop-around modes
Low power CMOS technology
Ordering Information
MT8920BE
28 Pin PDIP
MT8920BP
28 Pin PLCC
MT8920BS
28 Pin SOIC
MT8920BE1
28 Pin PDIP*
MT8920BP1
28 Pin PLCC*
MT8920BS1
28 Pin SOIC*
MT8920BPR1 28 Pin PLCC*
*PB Free Matte Tin
-40°C to 85°C
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
August 2005
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Description
The ST-BUS Parallel Access Circuit (STPA) provides
a simple interface between Zarlink’s ST-BUS and
parallel system environments.
Applications
•
•
•
•
•
Parallel control/data access to T1/CEPT digital
trunk interfaces
Digital signal processor interface to ST-BUS
Computer to Digital PABX link
Voice store and forward systems
Interprocessor communications
D7-D0
A4-A0
Tx0
Dual Port Ram
32 X 8
Parallel-
to-serial
Converter
STo0
CS
DS, OE
R/W, WE
DTACK,
BUSY, DCS
IRQ, 24/32
IACK, MS1
A5, STCH
MMS
Parallel
Port
Interface
Interrupt
Registers
Control
Registers
Rx0
Dual Port Ram
32 X 8
Serial-to-
Parallel
Converter
STi0
Tx1
Dual Port Ram
32 X 8
Parallel-
to-Serial
Converter
Comp/
MUX
Address
Generator
STo1
F0i
C4i
V
SS
V
DD
Figure 1 - Functional Block Diagram
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
1
MT8920B
STi0
IACK, MS1
F0i
C4i
VDD
MMS
DTACK,
BUSY, DCS
Data Sheet
28 PIN PDIP/SOIC
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
Name
C4i
F0i
Description
‡
4.096 MHz Clock.
The ST-BUS timing clock used to establish bit cell boundaries for the serial
bus.
Framing Pulse.
A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS
stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of
a frame.
Interrupt Acknowledge (Mode 1).
This active low input signals that the current bus cycle is
an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will
output a user-programmed vector number on D
0
- D
7
indicating the source of the interrupt.
Mode Select 1 (Mode 2,3).
This input is used to select the device operating modes. A low
applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)
ST-BUS Input 0.
This is the input for the 2048 kbit/s ST-BUS serial data stream.
Chip Select.
This active low input is used to select the STPA for a parallel access .
Data Strobe (Mode 1).
This active low input indicates to the STPA that valid data is on the data
bus during a write operation or that the STPA must output valid data on the data bus during a
read operation.
Output Enable (Mode 2).
This active low input enables the data bus driver outputs.
Output Enable (Mode 3).
This active low output indicates that the selected device is to be
read and that the data bus is available for data transfer.
Read/Write (Mode 1,2).
This input defines the data bus transfer as a read (R/W = 1) or a write
(R/W= 0) cycle.
Write Enable (Mode 3).
This active low output indicates the data on the data bus is to be
written into the selected location of an external device.
3
IACK
MS1
4
5
6
STi0
CS
DS
OE
OE
7
R/W
WE
8-12
A0-A4
Address Bus (Mode 1,2).
These inputs are used to select the internal registers and two-port
memories of the STPA.
A0-A4
Address Bus (Mode 3).
These address outputs are generated by the STPA and reflect the
position in internal RAM where the information will be fetched from or stored in. Addresses
generated in this mode are used to access external devices for direct memory transfer.
2
A4
A5, STCH
VSS
D0
D1
D2
D3
C4i
F0i
IACK, MS1
STi0
CS
DS, OE
R/W, WE
A0
A1
A2
A3
A4
A5, STCH
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
MMS
DTACK, BUSY, DCS
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
4
3
2
1
28
27
26
•
12
13
14
15
16
17
18
CS
DS, OE
R/W, WE
A0
A1
A2
A3
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
28 PIN J-LEAD
Data Sheet
Pin Description (continued)
Pin #
13
Name
A5
A5
Description
‡
MT8920B
Address Bit A5 (Mode 1).
This input is used to extend the address range of the STPA. A5
selects internal registers when high and Tx/Rx RAM’s when low.
Address Bit A5 (Mode 2).
This input is used to extend the address range of the STPA. A5
selects Tx0/Rx0 RAM’s when low and Tx1/Rx0 RAM’s when high.
STCH
Start of Channel (Mode 3).
This signal is a low going pulse which indicates the start of an
ST-BUS channel. The pulse is four bits wide and begins at the start of each valid channel.
14
15-22
23
24
V
SS
Ground.
D0-D7
Bidirectional Data Bus.
This bus is used to transfer data to or from the STPA during a write
or read operation.
STo0
STo1
ST-BUS Output 0.
This output supplies the output ST-BUS 2048 kbit/s serial data stream from
Tx0 two-port RAM.
ST-BUS Output 1.
In modes 1 and 2 this output supplies the output ST-BUS 2048 kbit/s serial
data stream from Tx1 two-port RAM. In mode 3, information arriving at STi0 is output here with
one frame delay.
Interrupt Request (Mode 1).
This open drain output, when low, indicates when an interrupt
condition has been raised within the STPA.
24 Channel/32 Channel Select (Mode 2,3).
This input is used to select the channel
configuration in modes 2 and 3. A low applied to this pin will select a 24 (T1) channel mode
while a high will select a 32 (CEPT) channel mode.
25
IRQ
24/32
26
DTACK
Data Transfer Acknowledge (Mode 1).
This open drain output is supplied by the STPA to
acknowledge the completion of data transfers back to the
µP.
On a read of the STPA, DTACK
low indicates that the STPA has put valid data on the data bus. On a write, DTACK low
indicates that the STPA has completed latching the
µP’s
data from the data bus.
BUSY
BUSY (Mode 2).
This open drain output signals that the controller and the ST-BUS are
accessing the same location in the dual-port RAM’s. It is intended to delay the controller
access until after the ST-BUS completes its access.
DCS
Delayed Chip Select (Mode 3).
This low going pulse, which is four bit cells long, is active
during the last half of a valid channel. This signal is used to daisy-chain together two STPA’s in
mode 3 that are accessing devices on the same parallel data bus.
Master Mode Select (Reset).
This Schmitt trigger input selects between either mode 1 (MMS
= 1), or modes 2and 3 (MMS = 0). If MMS is pulsed low in Mode 1 operation the control and
interrupt registers will be reset. (Refer to Table 1.) During power-up, the time constant of the
reset circuit (see Fig. 8) must be a minimum of five times the rise time of the power supply.
Power Supply Input.
(+5V).
Mode of
Operation
27
MMS
28
V
DD
MMS
MS1
‡ Pin Descriptions pertain to all modes unless otherwise stated.
Mode
Function
1
1
N/A
µ
P
Peripheral
Mode
Fast RAM
Mode
The STPA provides parallel-to-serial and serial-to-parallel conversions through a
68000-type interface. Two Tx RAMs and one Rx RAM are available along with full
interrupt capability. 32 channel or 24 channel support is available. Control Register 1, bit
D
5
(RAMCON) = 0 for 32 channel operation and D
5
(RAMCON)= 1 for 24 channel
operation.
The STPA provides a fast access interface to Tx0, Tx1 and Rx0 RAMs. This mode is
intended for full parallel support of 24 channel T1/ESF trunks and 32 channel CEPT
trunks. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32
channel operation.
The STPA will synchronously drive the parallel bus using the address generator and
provide all data transfer signals. This mode is intended to support 24 or 32 channel
devices in the absence of a parallel bus controller. Input 24/32 (pin 25) = 0 for 24 channel
operation, input 24/32 (pin 25) = 1 for 32 channel operation.
2
0
1
3
0
0
Bus
Controller
Mode
Table 1. STPA Modes of Operation
3
MT8920B
Functional Description
The STPA (ST-BUS Parallel Access) device provides
a simple interface between Zarlink’s ST-BUS and
parallel system environments. The ST-BUS is a
synchronous, time division, multiplexed serial
bussing scheme with data streams operating at 2048
kbit/s. The ST-BUS is the primary means of access
for voice, data and control information to Zarlink’s
family of digital telecommunications components,
including North American and European digital trunk
interfaces, ISDN U and S digital line interfaces, filter
codecs, rate adapters, etc. The STPA provides
several modes of operation optimized according to
the type of information being handled.
For interfacing parallel data and control information
to the ST-BUS, such as signalling and link control for
digital trunks, the STPA provides a
µP
access mode
(Mode 1), and looks like a 68000 type peripheral. In
this mode, the device provides powerful interrupt
features, useful in monitoring digital trunk or line
status (i.e., synchronization, alarms, etc.) or for
setting up message communication links between
microprocessors.
To interface high speed data or multi-channel voice/
data to the ST-BUS for switching or transmission, the
STPA has a high speed synchronous access mode
(Mode 2) and acts like a fast RAM. For voice storage
and forward, bulk data transfer, data buffering and
other similar applications, the STPA has a
controllerless mode (Mode 3) in which it provides
address and control signals to the parallel bus This
is useful for performing direct transfers to the
ST-BUS from external devices such as a RAM buffer.
The STPA is a two port device as shown in the
functional block diagram in Figure 1. The parallel
port provides direct access to three dual port RAM’s,
two transmit and one receive. The address, data
Data Sheet
and control busses are used to communicate
between the RAM‘s and a parallel environment.
Two
parallel-to-serial
converters,
and
one
serial-to-parallel converter interface the dual port
RAM’s to the ST-BUS port of the STPA. This port
consists of two serial output streams and one serial
input stream operating at 2048 kbit/s.
This
configuration of two outputs and one input was
designed to allow a single STPA to form a complete
control interface to Zarlink’s digital trunk interfaces
(MT8976, MT8978 and MT8979) which have two
serial input and one serial output control streams.
ST-BUS clocking circuitry, address generator and
various control and interrupt registers complete the
STPA’s functionality.
Modes of Operation
The three basic modes of operation,
µP
Peripheral
Mode (Mode 1), Fast RAM Mode (Mode 2) and Bus
Controller Mode (Mode 3) are selected using two
external input pins. These inputs are MMS and MS1
and are decoded as shown in Table 1. Whenever
MMS=1 the device resides in Mode 1. In this mode,
MS1 pin is unavailable and is used for a different
function.
When MMS=0, Modes 2 or 3 are selected as
determined by input MS1. If MS1=1, Mode 2 is
selected and if MS1 =0, Mode 3 is selected.
Each of the modes of the STPA provides a different
pinout to ease interfacing requirements of different
parallel environments. These are shown in Figure 3
below. In
µP
Peripheral Mode the device uses
interface signals consistent with a 68000-type
µP
bus. Mode 2, Fast RAM Mode, uses signals typical
of standard RAM type interfaces. Mode 3 interface
signals are very similiar to Mode 2 signals except
that the address and control signals are supplied as
outputs by the STPA.
Bus Controller Mode #3
VDD
MMS
BUSY
24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
C4i
F0i
MS1
STi0
CS
OE
WE
A0
A1
A2
A3
A4
STCH
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
MMS
DCS
24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
µP
Peripheral Mode #1
C4i
F0i
IACK
STi0
CS
DS
R/W
A0
A1
A2
A3
A4
A5
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
MMS
DTACK
IRQ
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
C4i
F0i
MS1
STi0
CS
OE
R/W
A0
A1
A2
A3
A4
A5
VSS
Fast RAM Mode #2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 3 - Modes 1, 2, 3 Pin Connections
4
Data Sheet
24/32 Channel Operation
The STPA may be configured to operate as a 32
channel or 24 channel device. This feature, which is
available in all three modes of operation, is
particularly useful in applications involving data
access to CEPT and T1 digital trunk interfaces.
When used as a data interface to Zarlink‘s CEPT
digital trunks, the STPA maps the 32 consecutive
bytes of each dual port memory directly to ST-BUS
channels 0-31. This is performed by the address
generator shown in the functional block diagram (see
Figure 1). Figures 4 c & d show the relationship
between relative dual port RAM locations and
corresponding ST-BUS channels, for both input and
output serial streams, when the STPA is configured
as a 32 channel device.
When used as a data interface to Zarlink’s T1 trunk
devices, however, only the first 24 consecutive RAM
locations are mapped to 24 of the 32 ST-BUS
channels. This mapping follows a specific pattern
which corresponds with the data streams used by
Zarlink‘s T1 products. Instead of a direct correlation
(as in 32 channel operation), the 24 consecutive
RAM locations are mapped to the ST-BUS with every
fourth channel, beginning at channel 0, set to FF
16
(ie. channel 0, 4, 8, 12, 16, 20, 24 and 28). Figures
4 a & b show the relationship between RAM
locations and ST-BUS channel configuration. This
feature allows the STPA to be interfaced directly to
Zarlink’s T1 trunk family.
When the STPA is operated in Mode 1, 24 and 32
channel configurations are selected using bit D
5
(RAMCON) in Control Register 1. D
5
= 0 selects 32
channel operation and D
5
= 1 selects 24 channel
operation. When the STPA is operated in Modes 2
or 3, however, the channel configuration is done
using input 24/32 (pin 25). When 24/32 = 1 the
device uses all 32 channels and when 24/32 = 0 it
uses 24.
Dual Port RAMS
Each of the three serial ST-BUS streams is
interfaced to the parallel bus through a 32 byte dual
port RAM. This allows parallel bus accesses to be
performed asynchronously while accesses at the
ST-BUS port are synchronous with ST-BUS clock.
As with any dual port RAM interface between two
asynchronous systems, the possibility of access
contention exists. The STPA minimizes this
occurrence by recognizing contention only when
accesses are performed at the same time for the
same 8-bit cell within the dual port RAM’s.
Furthermore, the probability of contention is
MT8920B
lessened since ST-BUS accesses require only the
last half cycle of C4i of every channel. When
contention does occur, priority is always given to the
ST-BUS access.
The STPA indicates this contention situation in a
different manner for Modes 1 and 2. In Mode 1, the
contention is masked by virtue of the "handshaking"
method used to transfer data on this 68000-type
interface.
Data Strobe (DS) and Data Transfer
Acknowledge (DTACK) control the exchange. If
contention should occur the device will delay
returning DTACK and thus stretch the bus cycle until
the
µP
access can be completed.
In Mode 2, if access is attempted during a
"contention window" the STPA will supply the
BUSY signal to delay the start of the bus cycle. This
“contention window” is defined as shown in Figure
16. The window exists during the last cycle of C4i
clock in each channel timeslot. Although ST-BUS
access is only required during the last half of this
clock period, the “contention window“ exists for the
entire clock period since a parallel access occurring
just prior to an ST-BUS access will not complete
before the ST-BUS access begins. Figure 16 further
shows four possible situations that may occur when
parallel accesses are attempted in and around the
“contention window”. Condition 1 indicates that an
access occurring prior to the contention window but
lasting into the first half of it will complete normally
with no contention arbitration. If the access should
extend past the first half of the contention window
and into the ST-BUS access period, the BUSY signal
will be generated. Conditions 3 and 4 show accesses
occurring inside
the contention window. These
accesses will result in BUSY becoming active
immediately after the access is initiated and
remaining active as shown in Figure 16.
Access contention is non-existent in Mode 3 since
the parallel bus signals, driven by the STPA, are
synchronized to the ST-BUS clocks.
Mode 1 -
µP
Peripheral Mode
In Mode 1, the STPA operates as an asynchronous
68000-type microprocessor peripheral. All three
dual-port RAMS (Tx0, Tx1, Rx0) are made available
and may be configured as 32 or 24 byte RAM’s. Also
available are the full complement of control and
interrupt registers. The address map for Mode 1 is
shown in Table 2.
The STPA, in Mode 1, uses signals CS, R/W, DS
(Data Strobe), DTACK (Data Acknowledge) IRQ, and
IACK (Interrupt Acknowledge) at the parallel interface.
The pinout of the device is shown in Figure 3.
5
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