MT9076
T1/E1/J1 3.3V Single Chip Transceiver
Preliminary Information
Features
•
•
Combined T1/E1/J1 framer and LIU, with PLL
and 3 HDLCs
In T1/J1 mode the LIU can recover signals
attenuated by up to 43dB (7000ft of 22 AWG
cable)
In E1 mode the LIU can recover signals
attenuated by up to 43dB (2200m of 0.65mm
cable)
Low jitter digital PLL (intrinsic jitter < 0.02UI)
HDLCs can be assigned to any timeslot
Comprehensive alarm detection, performance
monitoring and error insertion functions
2.048Mbit/s or 8.192Mbit/s ST-BUS streams
Support for Inverse Mux for ATM (IMA)
Support for V5.1 and V5.2 Access Networks
3.3V operation with 5V tolerant inputs
Intel or Motorola non-multiplexed 8-bit
microprocessor port
JTAG boundary scan
DS5289
ISSUE 1
January 2000
Ordering Information
MT9076AP
68 Pin PLCC
MT9076AB
80 Pin LQFP
-40 to +85°C
•
Description
The MT9076 is a highly featured single chip solution
for terminating T1/E1/J1 trunks. It contains a long-
haul LIU, an advanced framer, a high performance
PLL, and 3 HDLCs.
In T1 mode, the MT9076 supports D4, ESF and
SLC-96 formats meeting the latest recommendations
including AT&T PUB43801, TR-62411; ANSI T1.102,
T1.403 and T1.408; Telcordia GR-303-CORE.
In E1 mode, the MT9076 supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823, G.964 (V5.1), G.965
(V5.2) and I.431. It also supports ETSI ETS 300 011,
ETS 300 166, ETS 300 233, ETS 300 324 (V5.1) and
ETS 300 347 (V5.2).
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•
•
•
•
•
•
•
•
Applications
•
•
•
•
E1/T1 add/drop multiplexers
Access networks
Primary rate ISDN nodes
Digital Cross-connect Systems (DCS)
TxDL TxDLCLK
TxMF
TxAO TxB TxA
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
ST-BUS
Interface
IEEE
1149.1
Transmit Framing, Error,
Test Signal Generation and Slip Buffer
Pulse
Generator
Line
Driver
TTIP
TRING
National
Bit Buffer
Jitter Attenuator
& Clock Control
CAS
Buffer
Clock,Data
Recovery
DG Loop
MT
Loop
ST Loop
RM
Loop
PL Loop
Microprocessor
Interface
IRQ
D7~D0
AC4
S/FR
BS/LS
OSC1
OSC2
Data Link,
HDLC0
HDLC1
R/W/WR
CS
DS/RD
DSTo
CSTo
Rx Equalizer
& Data Slicer
AC0
RTIP
RRING
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxDLCLK RxDL
RxMF
/TxFP
LOS
RxFP
Exclk
F0b
C4b
Figure 1 - MT9076 Functional Block
1
MT9076
DSTi
DSTo
CSTi
CSTo
VDD4
VSS4
OSC2
OSC1
VSS3
VDD3
S/
FR
/Exclki
TxDL
TxDLCK
IC3
IC2
LOS
Preliminary Information
DS
/RD
8
CS
RESET
IRQ
D0
D1
D2
D3
VSS5
IC4
INT/MOT
VDD5
D4
D5
D6
D7
R/W/WR
AC0
10
12
14
16
18
20
22
24
26
28
6
4
2
68
66
64
62
60
58
56
54
TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD2
VSS2
IC1
RxFP
F0b
C4b
Exclk
68 PIN PLCC
52
50
48
46
44
30
32
34
36
38
40
42
NC
DS/RD
DSTi
DSTo
CSTi
CSTo
VDD4
VSS4
OSC2
OSC1
VSS3
VDD3
S/
FR
/Exclki
TXDL
TCDLCK
IC3
IC2
LOS
NC
NC
60
62
38
64
36
66
34
68
32
70
72
28
74
26
76
24
78
22
80
2
4
6
8
10
12
14
16
18
20
58
56
54
52
50
48
46
44
42
40
AC1
AC2
AC3
AC4
GNDARx
RTIP
RRING
VDDArx
VDD1
VSS1
TXA
TXB
RxDCLK
RxDL
TxMF
RxMF/TxFP
BS/
LS
NC
NC
CS
RESET
IRQ
D0
D1
D2
D3
VSS5
IC4
INT/MOT
VDD5
D4
D5
D6
D7
R/W/WR
AC0
NC
80 PIN LQFP
30
NC
NC
TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD2
VSS2
IC1
RxFP
F0b
C4b
Exclk
NC
NC
AC1
AC2
AC3
AC4
GNDARx
RTIP
RRING
VDARx
VDD1
VSS1
TXA
TXB
RXDLCK
RXDL
TxMF
RxMF/TxFP
BS/LS
Figure 2 - Pin Connections
2
NC
NC
Preliminary Information
Pin Description
Pin #
Name
PLCC LQFP
1
2
3
4
5
51
52
53
54
55
OSC1
OSC2
V
SS4
V
DD4
CSTo
Description
MT9076
Oscillator (3V Input).
This pin is either connected via a 20.000 MHz crystal to OSC2
where a crystal is used, or is directly driven when a 20.000 MHz. oscillator is employed.
Oscillator (3V Output).
Connect a 20.0 MHz crystal between OSC1 and OSC2. Not
suitable for driving other devices.
Negative Power Supply .
Digital ground.
Positive Power Supply .
Digital supply (+3.3V
±
5%).
Control ST-BUS (5V tolerant Output).
CSTo carries serial streams for CAS and CCS
respectively a 2.048 Mbit/s ST-BUS status stream which contains the 30 receive
signaling nibbles (ABCDZZZZ or ZZZZABCD). The most significant nibbles of each ST-
BUS time slot are valid and the least significant nibbles of each ST-BUS time slot are
tristated when control bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the
position of the valid and tristated nibbles are reversed.
Control ST-BUS (5V tolerant Input).
CSTi carries serial streams for CAS and CCS
respectively a 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit
signaling nibbles (ABCDXXXX or XXXXABCD) when RPSIG=0. When RPSIG=1 this
pin has no function. The most significant nibbles of each ST-BUS time slot are valid and
the least significant nibbles of each ST-BUS time slot are ignored when control bit MSN
(page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the valid and
ignored nibbles is reversed.
Data ST-BUS (5V tolerant Output).
A 2.048 Mbit/s serial stream which contains the
24/30 PCM(T1/E1) or data channels received on the PCM 24/30 (T1/E1) line.
Data ST-BUS (5V tolerant Input).
A 2.048 Mbit/s serial stream which contains the
24/30 (T1/E1) PCM or data channels to be transmitted on the PCM 24/30 (T1/E1)
line.
Data/Read Strobe (5V tolerant Input).
In Motorola mode (DS), this input is the active low data strobe of the processor
interface. In Intel mode (RD), this input is the active low read strobe of the processor
interface.
Chip Select (5V tolerant Input).
This active low input enables the non-multiplexed
parallel microprocessor interface of the MT9076. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
RESET (5V tolerant Input).
This active low input puts the MT9076 in a reset condition.
RESET should be set to high for normal operation. The MT9076 should be reset after
power-up. The RESET pin must be held low for a minimum of 1µsec. to reset the device
properly.
Interrupt Request (5V tolerant Output).
A low on this output pin indicates that an
interrupt request is presented. IRQ is an open drain output that should be connected to
V
DD
through a pull-up resistor. An active low CS signal is not required for this pin to
function.
Data 0 to Data 3 (5V tolerant Three-state I/O).
These signals combined with D4-D7
form the bidirectional data bus of the parallel processor interface (D0 is the least
significant bit).
Negative Power Supply.
Digital ground.
Internal Connection (3V Input).
Tie to V
SS
(Ground) for normal operation.
6
56
CSTi
7
8
57
58
DSTo
DSTi
9
59
DS/RD
10
63
CS
11
64
RESET
12
65
IRQ
13 - 66-69
16
17
18
70
71
D0 - D3
VSS5
IC4
3
MT9076
Pin Description (continued)
Pin #
Name
PLCC LQFP
19
72
Description
Preliminary Information
INT/MOT
Intel/Motorola Mode Selection (5V tolerant Input).
A high on this pin configures the
processor interface for the Intel parallel non-multiplexed bus type. A low configures the
processor interface for the Motorola parallel non-multiplexed type.
VDD5
D4 - D7
Positive Power Supply.
Digital supply (+3.3V
±
5%).
Data 4 to Data 7 (5V tolerant Three-state I/O).
These signals combined with D0-D3
form the bidirectional data bus of the parallel processor interface (D7 is the most
significant bit).
20
73
21 - 74-77
24
25
78
R/W/WR
Read/Write/Write Strobe (5V tolerant Input).
In Motorola mode (R/W), this input
controls the direction of the data bus D[0:7] during a microprocessor access. When R/W
is high, the parallel processor is reading data from the MT9076. When low, the parallel
processor is writing data to the MT9076. For Intel mode (WR), this active low write
strobe configures the data bus lines as output.
AC0 - AC4
Address/Control 0 to 4 (5V tolerant Inputs).
Address and control inputs for the
non-multiplexed parallel processor interface. AC0 is the least significant input.
GNDARx
Receive Analog Ground.
Analog ground for the LIU receiver.
RTIP
RRING
Receive TIP and RING (3V Input).
Differential inputs for the receive line signal - must
be transformer coupled (See Figure 6). In digital framer mode these pins accept digital
3 volt signals from a physical layer device. They may accept a split phase unipolar
signal (RTIP and RRING employed) or an NRZ signal (RTIP only used).
Positive Power Supply.
Digital supply (+3.3V
±
5%).
Negative Power Supply.
Digital ground.
Transmit A (5V tolerant Output).
When the internal LIU is disabled (digital framer
only mode), if control bit NRZ=1, an NRZ output data is clocked out on pin TxA with the
rising edge of Exclk (TxB has no function when NRZ format is selected). If NRZ=0, pins
TxA and TxB are a complementary pair of signals that output digital dual-rail data
clocked out with the rising edge of Exclk.
Transmit B (5V tolerant Output).
When the internal LIU is disabled and control bit
NRZ=0, pins TxA and TxB are a complementary pair of signals that output digital dual-
rail data clocked out with the rising edge of Exclk.
26 -
30
31
32
33
79,
2-5
6
7
8
34
35
36
37
9
10
11
12
VDDARx
Receive Analog Power Supply.
Analog supply for the LIU receiver (+3.3V
±
5%).
VDD1
VSS1
TxA
38
13
TxB
39
14
RxDLCLK
Data Link Clock (5V tolerant Output).
A gapped clock signal derived from the
extracted line clock, available for an external device to clock in RxDL data (at 4, 8, 12,
16 or 20 kHz) on the rising edge.
RxDL
TxMF
Receive Data Link (5V tolerant Output).
A serial bit stream containing received line
data after zero code suppression. This data is clocked out with the rising edge of Exclk.
Transmit Multiframe Boundary (5V tolerant Input).
An active low input used to set
the transmit multiframe boundary (CAS or CRC multiframe). The MT9076 will generate
its own multiframe if this pin is held high. This input is usually pulled high for most
applications.
40
41
15
16
4
Preliminary Information
Pin Description (continued)
Pin #
Name
PLCC LQFP
42
17
RxMF/
TxFP
Description
MT9076
Receive Multiframe Boundary / Transmit Frame Boundary (5V tolerant Output).
If
the control bit Tx8KEN (page 02H address 10H bit 2) is low, this negative output pulse
delimits the received multiframe boundary. The next frame output on the data stream
(DSTo) is basic frame zero on the T1 or PCM 30 link. In E1 mode this receive
multiframe signal can be related to either the receive CRC multiframe (page 01H,
address 17H, bit 6, MFSEL=1) or the receive signaling multiframe (MFSEL=0). If the
control bit Tx8KEN is set high, this positive output pulse delimits the frame boundary
(the first bit transmit in the frame) for the digital output stream on pins TXA and TXB.
Bus/Line Syncronization Mode Selection (5V tolerant Input).
If high, C4b and F0b
will be inputs; if low, C4b and F0b will be outputs.
2.048 MHz in E1 mode or 1.544MHz in T1 mode, Extracted Clock (5V tolerant
Output).
The clock extracted from the received signal and used internally to clock in
data received on RTIP and RRING.
4.096 MHz System Clock (5V tolerant Input/Output).
C4b is the clock for the ST-BUS
sections and transmit serial PCM data of the MT9076. In the free-run (S/FR/Exclki=0) or
line synchronous mode (S/FR/Exclki=1 and BS/LS=0) this signal is an output, while in
bus synchronous mode (S/FR/Exclki=1 and BS/LS=1) this signal is an input clock.
Frame Pulse (5V tolerant Input/Output).
This is the ST-BUS frame synchronization
signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the
PCM30 link. In the free-run (S/FR/Exclki=0) or line synchronous mode (S/FR/Exclki=1
and BS/LS=0) this signal is an output, while in bus synchronous mode (S/FR/Exclki=1
and BS/LS=1) this signal is an input.
Receive Frame Pulse/Receive CCS Clock (5V tolerant Output).
An 8kHz pulse
signal, which is low for one extracted clock period. This signal is synchronized to the
receive DS1 or PCM 30 basic frame boundary.
Internal Connection.
Must be left open for normal operation.
Negative Power Supply.
Digital ground.
Positive Power Supply.
Digital supply (+3.3V
±
5%).
Transmit Analog Power Supply.
Analog supply for the LIU transmitter (+3.3V
±5%).
Transmit TIP and RING(Output).
Differential outputs for the transmit line signal - must
be transformer coupled (See Figure 6).
Transmit Analog Ground .
Analog ground for the LIU transmitter.
IEEE 1149.1a Test Data Input (3V Input).
If not used, this pin should be pulled high.
IEEE 1149.1a Test Data Output (5V tolerant Output).
If not used, this pin should be
left unconnected.
IEEE 1149.1a Test Mode Selection (3V Input).
If not used, this pin should be pulled
high.
IEEE 1149.1a Test Clock Signal (3V Input).
If not used, this pin should be pulled high.
IEEE 1149.1a Reset Signal (3V Input).
If not used, this pin should be held low.
Transmit All Ones (Input).
High - TTIP, TRING will transmit data normally. Low - TTIP,
TRING will transmit an all ones signal.
43
44
18
22
BS/LS
Exclk
45
23
C4b
46
24
F0b
47
25
RxFP
48
49
50
51
52
53
54
55
56
57
58
59
60
26
27
28
29
30
31
32
33
34
35
36
37
38
IC1
V
SS2
V
DD2
VDD
ATx
TTIP
TRING
GND
ATx
Tdi
Tdo
Tms
Tclk
Trst
TxAO
5
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