SDC-361/362
16-BIT, TWO SPEED SYNCHRO-TO-DIGITAL
AND RESOLVER-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
The SDC-361 is a low-cost, single
module synchro-to-digital (S/D) and
resolver-to-digital (R/D) tracking con-
verter. A unique control transformer
algorithm is used that provides inher-
ently higher accuracy and jitter-free
output. Other features include a BIT
logic signal to indicate proper tracking
and an analog velocity output.
Utilizing a type II servo loop, these
converters have no velocity lag up to
the specified tracking rate, and output
data is always fresh and continuously
available. Each unit is fully trimmed
and requires no adjustment.
APPLICATIONS
The SDC-361 may be used wherever
analog angle data from synchros or
resolvers must be converted rapidly
and accurately to digital form for
transmission, storage and analysis.
Because these units are extremely
rugged and stable, and meet the
requirements of MIL-STD-202E, they
are suitable for the most severe
industrial, commercial and military
applications. Military ground support
and avionics uses include ordnance
control, radar tracking systems, navi-
gation and collision avoidance sys-
tems.
•
Accuracy: ±1 LSB = ±20 Seconds
•
SIGNAL AND REF INPUTS:
- Internal Transformer Isolation
- Broadband Input: 350-3000 Hz
or 47-3000 Hz
- All common L-L voltage levels
•
LOGIC:
- TTL Compatible
- 16-Bit Parallel Binary Angle
Output, and Converter Busy,
Inhibit and BIT
•
POWER REQUIREMENTS:
- ±15 VDC and +5 VDC
SIN (θ -
φ)
SIN 36 (θ -
φ)
36X
SYNCHRO
INPUT
S1
S2
S3
SCOTT-T
TRANSFORMER
CONTROL
TRANSFORMER
CT
COS 36θ
36
φ
36X OR 1X RESOLVER INPUT OPTION:
S1
RESOLVER S2
INPUT S3
S4
RESOLVER
ISOLATION
TRANSFORMER
SIN
θ
COS
θ
16 BIT
UP-DOWN COUNTER
(CONTAINS ANGLE
φ)
φ
φ
36X DIGITAL
MULTIPLIER
SIN 36θ
STICKOFF
-
+
CROSS-OVER
DETECTOR
ERROR
R
(θ -
φ)
ERROR PROCESSOR
AND VOLTAGE
CONTROLLED
OSCILLATOR
REFERENCE
ISOLATION
TRANSFORMER
RH REF
RL INPUT
VEL VELOCITY
INH INHIBIT
CB CONVERTER
BUSY
DIGITAL OUTPUT
φ
BITS 1to 16
1X
SYNCHRO
INPUT
S1
S2
S3
SCOTT-T
TRANSFORMER
SIN
θ
COS
θ
CONTROL
TRANSFORMER
CT
SIN
(θ − φ
+2.5˚)
CONTAINS 2.5˚
ANGLE OFFSET
NOTE: Block Diagram Illustrates
SDC-361. All References to "36X"
are "18X" for SDC-362.
FIGURE 1. BLOCK DIAGRAM
©
1980, 1999 Data Device Corporation
TABLE 1. SDC-361/362
PARAMETER
RESOLUTION
ACCURACY
SDC-361
SDC-362
SIGNAL AND REFERENCE INPUT
(All inputs transformer isolated.
Other freq. and volt. available.on
special order. )
Synchro Input
90V L-L, 400 Hz (Option H)
90V L-L, 60 Hz (Option I)
11.8V L-L, 400 Hz (Option L)
Resolver Input
90V L-L, 400 Hz (Option H)
26V L-L, 400 Hz (Option I)
11.8V L-L, 400 Hz (Option L)
SPECIFICATIONS
VALUE
16 bits
±1 LSB ( 20 sec)
±1 LSB ( 40 sec)
Signal
Frequency
Range
Signal Input
Impedance
(L-L Balanced,
Resistive)
148 Kohm min
148 Kohm min
19 Kohm min
148 Kohm min
42 Kohm min
19 Kohm min
Reference Input
Impedance
(L-L Balanced,
Resistive)
300 Kohm min
80 Kohm min
TABLE 1. SDC-361/362 SPECIFICATIONS (CONTD)
VALUE
PARAMETER
DYNAMIC CHARACTERISTICS
(Continued)
Velocity Constant
(Type II Servo Loop)
Acceleration Constant
Options H, M, L ( 400 Hz)
Option I ( 60 Hz)
POWER SUPPLIES
Nominal Value
Voltage Range
Max Voltage without Damage
Current
Typical
Maximum
TEMPERATURE RANGES
Operating
-1 Option
-3 Option
Storage
PHYSICAL CHARACTERISTICS
Size
3.125 x 2.625 x 0.82 inches
(79.4 x 66.7 x 20.8 mm)
7 oz
(200 g)
Kv =
∞
K
A
= 70,000 Nominal
K
A
= 4,300 Nominal
350-3000 Hz
47-3000 Hz
350-3000 Hz
350-3000 Hz
350-3000 Hz
350-3000 Hz
Reference
Frequency
Range
+15 V
+11.5 to
+16.5 V
+18 V
10 mA
15 mA
-15 V
-11 to
-16.5 V
-18 V
35 mA
50 mA
+5 V
+ 4.5 to
+ 5.5 V
+7 V
110 mA
150 mA
-55°C to + 105°C
0°C to + 70°C
-55°C to + 125°C
Reference Input
(Option H, I )
(Option M, L)
DIGITAL INPUT/OUTPUT
Logic Type
Inhibit Input (INH) Loading
40-150 V rms
10- 50 V rms
TTL
Logic “0” inhibits, 0.2 Std TTL
loads plus 18 Kohm min
pull-up resistor to +5 V supply.
Natural binary angle; pos. logic
1-2.5 µsec positive pulse,
data changes on leading edge
2 Std TTL loads (Consult factory
for 5 Std load capability)
Logic 0 = normal tracking
Logic 1 = not tracking within
fine speed range
±1.0 VDC ±30% for 100°/sec
at 400 Hz
±1.0 VDC ±30% for 25°/sec
at 60 Hz
±10 VDC min
±10 Kohm max
Weight
Outputs
16 Parallel data Bits
Converter Busy (CB)
Drive Capabilitity
BIT (Bilt In Test)
INTRODUCTION
The operation of a two speed S/D is essentially the same as a
single speed module, except there are two control transformers
(CT) which generate two error voltages. These two CTs are fed
by a common up-down counter. The counter data is multiplied by
36 for an SDC-361 and 18 for an SDC-362 to generate the fine
speed CT. Assuming an off-null condition as when the system is
initially energized, the crossover detector feeds the coarse (1X)
CT error signal output to the demodulator and error processor.
The converter seeks a null as it would for a single speed S/D. As
null is approached (to within 2.5° nominally) the coarse CT out-
put drops below a preset threshold and the crossover detector
then switches the fine CT error signal (36X for SDC-361, 18X for
SDC-362) into the demodulator and error processor.
Since the counter angle
θ
is multiplied by 36X for SDC-361, and
18X for SDC-362, the gradient of the fine speed CT is 36X the
coarse output CT for the SDC-361, and 18X for the coarse out-
put CT for the SDC-362. The servo loop then seeks a finer null,
using the fine speed CT error signal. The converter continues to
use the fine error signal for continuous tracking, and only switch-
es back to the coarse signal when the coarse error exceeds the
crossover threshold. To eliminate false stable nulls at 180°, an
angle offset and stickoff voltage are introduced in the coarse
channel. The ±15 V power supplies can vary over their specified
ranges with no change in the converter specifications except for
a proportional change in the maximum ± tracking rates. When
testing or evaluating the converters, it is advisable to limit the
current to each of the three power supplies. Set each current
limit to 50% greater than the maximum current listed for that sup-
ply in TABLE 1.
2
ANGULAR VELOCITY OUTPUT
Scale Factor
Range
Loading
DYNAMIC CHARACTERISTICS
Input Rate for Full Velocity
Options H, M, L (400 Hz)
Option I (60 Hz)
Acceleration for 1 LSB Lag
Options H, M, L(400 Hz)
Option I ( 60 Hz)
Settling Time
For Normal Tracking
(Up to specified Input Rate)
For 179° Step Change
(Typical Values)
Options H, M, L (400 Hz)
Settling to 1 LSB
Settling to Final Value
Options I (60 Hz)
Settling to 1 LSB
Settling to Final Value
0-1000°/sec minimum
0-250°/sec minimum
384°/sec² typ
23°/sec² typ
No Lag Error
400 msec
480 msec
1400 msec
1800 msec
To prevent damage to the input transformers, the maximum volt-
age should not exceed the specified input voltage by more than
30%. The maximum common mode voltage (DC plus recurrent
AC peak) should not exceed 500 V.
ANALOG VELOCITY OUTPUT
VEL is a DC voltage proportional to the angular velocity dθ/dt =
dφ/dt. The output is derived from an op-amp with low output
impedance and is short-circuit protected. Other characteristics
are listed in TABLE 1.
DIGITAL INPUTS
Logic inputs are low power Schottky and the can drive remote
loads. The BIT logic output is a built-in-test derived from the
crossover detector. It goes to logic 1 whenever the digital output
is not tracking the input signal within the range of the fine speed
synchro or resolver.
TABLE 2. BIT WEIGHT
BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEG/BIT
180
90
45
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10,800
5,400
2,700
1,350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
.66
.33
DYNAMIC PERFORMANCE
A Type II servo loop (Kv =
∞)
and very large acceleration con-
stants give these converters superior dynamic performance, as
listed in TABLE 1. If the power supply voltages are not the ±15
VDC nominal values, the specified input rates for full accuracy
will increase or decrease in proportion to the fractional change in
voltage. The +15 V supply voltage will determine the maximum
positive velocity. The -15 V supply voltage will determine the
maximum negative velocity.
As long as the maximum tracking rate is not exceeded, there will
be no lag in the converter output. If a step input occurs, as is
likely when the power is initially turned on, the response will be
critically damped. After initial slewing at the maximum tracking
rate of the converter, there is one overshoot which is inherent to
a Type II servo. The overshoot settling to final value is a function
of the small signal settling time.
The loop dynamics of DDC’s tracking S/D converters are
described by the unity feedback configuration shown. The
closed-loop transient response is nominally critically damped,
and all loop dynamics can be determined from the diagram and
formulas given.
TIMING
Whenever an input signal change occurs, the converter changes
the digital angle in steps of 1 LSB, and generates a converter
busy pulse (CB). The output data change is initiated at the lead-
ing edge of the CB pulse, and the output is stable within 0.2 µsec
after the leading edge. Extra CB pulses will not occur if the input
angle changes while the counter is locked by the INH. The sim-
plest method of interfacing with a computer is to transfer data at
a fixed time interval after the inhibit is applied. The converter will
ignore an inhibit applied during the “busy” interval until that inter-
val is over. Timing is as follows: (a) apply the inhibit, (b) wait 0.2
µsec, (c) transfer the data and (d) release the inhibit.
θ
2
OVERSHOOT
θ
1
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
FIGURE 3. STEP RESPONSE INPUT
+
ANGLE
INPUT
e
G
DIGITAL
OUTPUT
5.5 µsec MIN
DEPENDS ON dθ/dt
CONVERTER “ 1 “
BUSY (CB)
“0“
1-2.5 µsec
INHIBIT
(INH)
“1“
“0“
DATA
VALID
0.2 µsec
VALID
–
UNITY FEEDBACK
1
At 60 Hz
At 400 Hz
66
2
G=
S
2
(
(
S
33
+ 1)
G=
266
2
S
2
(
(
S + 1)
133
S + 1)
1330
S + 1)
330
TABLE 2. TIMING DIAGRAM
FIGURE 4. S/D CONVERTER LOOP DYNAMICS
3
ACCURACY TESTS
Because of the accuracy of DDC’s S/D converters, only labora-
tory grade synchro or resolver substitution boxes or standards
should be used. If synchro standards are not available, arrange-
ments may be made to witness the final source inspection at the
DDC factory. The figure below shows how to setup equipment to
measure S/D converter accuracy. A separate lamp driver or suit-
able readout is required for each output data line. The synchro
standard is set to any desired test angle, and the lamps which
are lit are added according to their bit weights and compared with
the test angle.
TEST METHODS FOR DISCRETE MODULES
All of DDC’s discrete S/D converter modules are high quality
products whose semiconductor components are hermetically
sealed. Discrete modules will meet specific test methods and
conditions of MIL-STD-202E shown below unless alternate
methods are specified by the customer in his procurement doc-
umentation.
TABLE 4. MIL-STD-202E TEST METHODS
CONDITION
METHOD
204C
C
213B
A
106D *
--
107D
A
101D
B
105C
B
* when conformally coated on
COMMENT
10G, 2000 Hz vibration
50G, 11 ms shock
Moisture
Thermal shock
Salt spray
50,000 ft, altitude
P.C. board
PRINTED CIRCUIT BOARD MOUNTING
When mounting a converter on a printed circuit board, it is very
important to keep logic-level signals as far away from AC and
power signal as possible. Under no circumstances should AC or
power pins be adjacent to data pins at the connector. It is also
prudent to keep the AC and power pins separated from each
other. The intent is to make it impossible to short logic inputs/out-
puts to AC or power pins with scope probes, and to keep digital
noise from coupling into the sensitive AC signals.
It is strongly recommended that circuit layouts be designed so
plated through-holes are not required to mount hybrid or discrete
modules. If all lands connecting to pins are located on the oppo-
site (dip) side of the PC board from the module, there will be no
risk of destroying a connection by ripping out the plated through-
hole connection if the module must be replaced. It will also be
easier to unsolder the module without the module being dam-
aged.
REFERENCE
RH
RL
S/D OR R/D
CONVERTER
BEING
TESTED
SYNCHRO
OR
RESOLVER
INPUT
BIT I
LAMP DRIVER
BIT N
LAMP DRIVER
SYNCHRO/
RESOLVER
STANDARD
(SINGLE SPEED
OR TWO SPEED)
FIGURE 5. ACCURACY TEST CIRCUIT
4
2.625 ± .015
(66.7 ± 0.4)
BIT
VEL
CB
INH
*36X S4
36X S1
36X S3
36X S2
RL
RH
26 SPACES @
.100 ± .010 = 2.600
(2.5 ± 0.3 = 66.0)
(TOL. NON-CUM.)
.262 ± .020
(6.7 ± .051)
.100 (2.54)
(TYP)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1X S3
1X S1
1X S2
*1X S4
3.125 ± .015
(79.3 ± 0.4)
.025 ± .001
(0.6 ± 0.03)
SQUARE PIN
(TYP)
+15V
-15V
GND
+5V
.162 ± .020
(4.1 ± 0.5)
2.300 ± .010
(58.4 ± 0.3)
.250 (6.4)
(MIN)
.82(21)
(MAX)
BOTTOM
VIEW
Notes:
1. All reference to 36X become 18X on SDC-362.
2. Pin labels for reference only.
3. All dimensions shown in inches (mm).
4. Pin material meets solderability requirements of
MIL-STD-202E, Method 208C.
5. Case material is glass filled Diallyl Phthalate
per MIL-M-14, Type SDG-F.
6. S4 pins are present on resolver units only.
FIGURE 6. MECHANICAL OUTLINE
ORDERING INFORMATION
SDC-361-H-I
Temperature Range
1 = –55° to +105°C
3 = 0° to +70°C
Signal Input Voltage and Frequency
H = 90 V L-L, 400 Hz (Synchro or Resolver)
I = 90 V L-L, 60 Hz (Synchro only)
M = 26 V L-L, 400 Hz (Resolver only)
L = 11.8 V L-L, 400 Hz (Synchro or Resolver)
Speed
361 = 1 x 36 speed
362 = 1 x 18 speed
Input Type
SDC = Synchro
RDC = Resolver
5
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