®
ISO
2
-CMOS
MT9160
5 Volt Multi-Featured Codec (MFC)
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
Programmable
µ-Law/A-Law
Codec and Filters
Programmable CCITT (G.711)/sign-magnitude
coding
Programmable transmit, receive and side-tone
gains
Fully differential interface to handset
transducers - including 300 ohm receiver driver
Flexible digital interface including ST-BUS/SSI
Serial microport or default controllerless mode
Single 5 volt supply
Low power operation
CCITT G.714 compliant
ISSUE 3
May 1995
Ordering Information
MT9160AE
MT9160AS
24 Pin Plastic DIP
20 Pin SOIC
-40°C to +85°C
Description
The MT9160 5V Multi-featured Codec incorporates a
built-in Filter/Codec, gain control and programmable
sidetone path as well as on-chip anti-alias filters,
reference voltage and bias source. The device
supports both A-Law and
µ-Law
requirements.
Complete telephony interfaces are provided for
connection to handset transducers. Internal register
access is provided through a serial microport
compatible
with
various
industry
standard
micro-controllers.
The device also supports
controllerless operation utilizing the default register
conditions.
The MT9160 is fabricated in Mitel's ISO
2
-CMOS
technology ensuring low power consumption and
high reliability.
Applications
•
•
•
•
•
Digital telephone sets
Cellular radio sets
Local area communications stations
Pair Gain Systems
Line cards
VSSD
VDD
VSSA
VBias
VRef
FILTER/CODEC GAIN
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
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ENCODER
7dB
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AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
DECODER -7dB
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
M-
M+
Transducer
Interface
HSPKR +
HSPKR -
Din
Dout
STB/F0i
CLOCKin
Flexible
Digital
Interface
Timing
ST-BUS
C&D
Channels
Serial Microport
A/µ/IRQ
PWRST
IC
CS
DATA1
DATA2
SCLK
Figure 1 - Functional Block Diagram
7-77
MT9160
Preliminary Information
20 PIN SOIC
VBias
VRef
PWRST
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
M+
M-
VSSA
HSPKR +
HSPKR -
VDD
CLOCKin
STB/F0i
Din
Dout
24 PIN PDIP
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
NC
SCLK
DATA1
DATA2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
M+
M-
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
NC
STB/F0i
Din
Dout
Figure 2 - Pin Connections
Pin Description
Pin #
SOIC DIP
1
2
3
4
5
1
2
4
5
6
Name
V
Bias
V
Ref
PWRST
IC
A/µ/IRQ
Description
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1 µF capacitor to V
SSA
.
Reference Voltage for Codec (Output).
Nominally [(V
DD
/2)-1.5] volts. Used
internally. Connect 0.1 µF capacitor to V
SSA
.
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
Internal Connection.
Tie externally to V
SS
for normal operation.
A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs
the companding law used by the filter/Codec;
µ-Law
when tied to V
SS
and A-Law
when tied to V
DD
. Logically OR’ed with A/µ register bit.
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
Digital Ground.
Nominally 0 volts.
Chip Select (Input).
This input signal is used to select the device for microport data
transfers. Active low. TTL level compatible.
Serial Port Synchronous Clock (Input).
Data clock for microport. TTL level
compatible.
Bidirectional Serial Data.
Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input TTL level compatible.
Serial Data Receive.
In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input TTL level compatible.
6
7
8
9
7
8
10
11
V
SSD
CS
SCLK
DATA 1
10
12
DATA 2
7-78
Preliminary Information
Pin Description (continued)
Pin #
SOIC DIP
11
13
Name
D
out
Description
MT9160
Data Output.
A high impedance three-state digital output for 8 bit wide channel data
being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with
the rising edge of the bit clock during the timeslot defined by STB, or according to
standard ST-BUS timing.
Data Input.
A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
Data Strobe/Frame Pulse (Input).
For SSI mode this input determines the 8 bit
timeslot used by the device for both transmit and receive data. This active high signal
has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS
mode (refer to Figure 11). CMOS level compatible input.
12
14
D
in
13
15
STB/F0i
14
17
CLOCKin
Clock (Input).
(CMOS level compatible). The clock provided to this input pin is used
for the internal device functions. For SSI mode connect the bit clock to this pin when
it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit
clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin.
V
DD
Positive Power Supply (Input).
Nominally 5 volts.
15
16
17
18
19
20
18
19
20
22
23
24
3,9,
16,21
HSPKR-
Inverting Handset Speaker (Output).
Output to the handset speaker (balanced).
HSPKR+
Non-Inverting Handset Speaker (Output).
Output to the handset speaker
(balanced).
V
SSA
M-
M+
NC
Analog Ground (Input).
Nominally 0 volts.
Inverting Microphone (Input).
Inverting input to microphone amplifier from the
handset microphone.
Non-Inverting Microphone (Input).
Non-inverting input to microphone amplifier
from the handset microphone.
No Connect.
(DIP Package only).
7-79
MT9160
Overview
The 5V Multi-featured Codec (MFC) features
complete
Analog/Digital
and
Digital/Analog
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.
Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51
®
,
Motorola SPI
®
and National Semiconductor
Microwire
®
specifications.
These
parameters
include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.
Preliminary Information
design. This fully differential architecture is
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.
A reference voltage (V
Ref
), for the conversion
requirements of the Codec section, and a bias
voltage (V
Bias
), for biasing the internal analog
sections, are both generated on-chip. V
Bias
is also
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1µF
capacitor must be connected from V
Bias
to analog
ground at all times. Likewise, although V
Ref
may only
be used internally, a 0.1µF capacitor from the V
Ref
pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V
Ref
and V
Bias
pins are situated on adjacent pins.
The transmit filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0 dB). Gain control allows the output
signal to be increased up to 7 dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7 dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.
Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).
Transmit and receive filter gains are controlled by the
TxFG
0
-TxFG
2
and RxFG
0
-RxFG
2
control bits,
respectively. These are located in Gain Control
Register 1 (address 00h). Transmit filter gain is
adjustable from 0 dB to +7 dB and receive filter gain
from 0dB to -7 dB, both in 1 dB increments.
Side-tone filter gain is controlled by the STG
0
-STG
2
control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from
-9.96 dB to +9.96 dB in 3.32 dB increments.
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are CCITT
G.711 A-law or
µ-Law,
with true-sign/ Alternate Digit
Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign- magnitude coding may
also be selected for proprietary applications.
The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT9160.
In the event of PWRST, the MT9160 defaults such
that the side-tone path is off, all programmable gains
are set to 0dB and CCITT
µ-Law
is selected. Further,
the digital port is set to SSI mode operation at 2048
kb/s and the FDI and driver sections are powered up.
(See Microport section.)
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
Intel® and MCS-51® are registered trademarks of Intel Corporation
Motorola® and SPI® are registered trademarks of Motorola Corporation
National® and Microwire® are trademarks of National Semiconductor Corporation
7-80
Preliminary Information
Companding law selection for the Filter/Codec is
provided by the A/µ companding control bit while
the coding scheme is controlled by the Smag/CCITT
control bit. The A/µ control bit is logically OR’ed with
the A/µ pin providing access in both controller and
controllerless modes. Both A/µ and Smag/CCITT
reside in Control Register 2 (address 04h). Table 1
illustrates these choices.
CCITT (G.711)
µ-Law
1000 0000
1111 1111
0111 1111
0000 0000
MT9160
Control of this gain is provided by the TxINC
control bit (Gain Control register 1, address 00h).
• The handset speaker outputs (receiver), pins
HSPKR+/HSPKR-. This internally compensated
fully differential output driver is capable of driving
the load shown in Figure 4. The nominal handset
receive path gain may be adjusted to either 0 dB,
-6 dB or -12 dB. Control of this gain is provided
by the RxINC control bit (Gain Control register 1,
address 00h). This gain adjustment is in addition
to the programmable gain provided by the receive
filter.
Code
+ Full Scale
+ Zero
-Zero
(quiet code)
- Full Scale
Sign/
Magnitude
1111 1111
1000 0000
0000 0000
0111 1111
A-Law
1010 1010
1101 0101
0101 0101
HSPKR +
0010 1010
75
Ω
Table 1
Transducer Interfaces
MT9160
150 ohm
load
(speaker)
Standard handset transducer interfaces are provided
by the MT9160. These are:
• The handset microphone inputs (transmitter),
pins M+/M-. The nominal transmit amplifier gain
may be adjusted to either 6.0 dB or 15.3 dB.
75
Ω
HSPKR -
Figure 4 - Handset Speaker Driver
Serial Port
Filter/Codec and Transducer Interface
Default Bypass
Receive
Filter Gain
0 to -7 dB
(1 dB steps)
-6.0 dB or
0 dB
Receiver
Driver
HSPKR +
75Ω
HSPKR -
75Ω
Handset
Receiver
(150Ω)
PCM
D
in
-6 dB
Side-tone
-9.96 to
+9. 96 dB
(3.32 dB steps)
-11 dB
PCM
D
out
Default Side-tone off
Transmit Filter
Transmit Filter
Gain
Gain
0 to +7 dB
0 to +7 dB
(1 dB steps)
(1 dB steps)
Transmit Gain
-0.37 dB or 8.93 dB
Transmit
Gain
6.37 dB
M+
M-
Transmitter
Microphone
INTERNAL TO DEVICE
EXTERNAL TO DEVICE
Figure 3 - Audio Gain Partitioning
7-81
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