LOW SKEW, 1-TO-6 LVCMOS/LVTTL
CLOCK MULTIPLIER/ZERO DELAY BUFFER
ICS87931I-147
G
ENERAL
D
ESCRIPTION
The ICS87931I-147 is a low voltage, low skew
LVCMOS/LVTTL Clock Multiplier/ Zero Delay
HiPerClockS™
Buffer and a member of the HiPerClock ™
S
family of High Performance Clock Solutions from
ICS. With output frequencies up to 240MHz, the
ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I-147 contains
frequency configurable outputs and an external feedback in-
put for regenerating clocks with “zero delay”.
F
EATURES
•
Fully integrated PLL
•
Six LVCMOS/LVTTL outputs, 7Ω typical output impedance
•
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock
for redundant clock applications
•
Maximum output frequency: 240MHz
•
VCO range: 220MHz to 480MHz
•
External feedback for “zero delay” clock regeneration
•
Output skew: 165ps (maximum)
•
Cycle-to-cycle jitter: 45ps (maximum)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
DIV_SELC
DIV_SELB
DIV_SELA
IC
S
Selectable clock inputs, CLK1 and differential CLK0, nCLK0
support redundant clock applications. The CLK_SEL input de-
termines which reference clock is used. The output divider val-
ues of Bank A, B and C are controlled by the DIV_SELA,
DIV_SELB and DIV_SELC, respectively.
For test and system debug purposes, the PLL_SEL input al-
lows the PLL to be bypassed. When LOW, the nMR input re-
sets the internal dividers and forces the outputs to the high
impedance state.
The effective fanout of the ICS87931I-147 can be increased to
12 by utilizing the ability of each output to drive two series
terminated transmission lines.
P
IN
A
SSIGNMENT
nc
GND
32 31 30 29 28 27 26 25
nc
V
DDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
1
2
3
4
5
6
7
8
24
23
GND
QB0
QB1
V
DDO
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
ICS87931I-147
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
9 10 11 12 13 14 15 16
V
DDO
QA0
QA1
22
21
20
19
18
17
B
LOCK
D
IAGRAM
POWER_DN
Pullup
PLL_SEL
Pullup
CLK_SEL
Pulldown
CLK1
Pullup
GND
nc
CLK_EN0
CLK_EN1
EXT_FB
V
DDO
QC0
QC1
GND
CLK0
Pullup
nCLK0
None
EXTFB_SEL
EXT_FB
Pulldown
Pullup
1
0
PHASE
DETECTOR
LPF
1
0
÷8
VCO
0
0
1
÷2
1
÷2/÷4
QA0
QA1
÷2/÷4
QB0
QB1
DIV_SELA
Pulldown
DIV_SELB
Pulldown
CLK_EN0
Pullup
CLK_EN1
Pullup
DIV_SELC
Pulldown
nMR
Pullup
POWER-ON RESET
÷4/÷6
DISABLE
LOGIC
QC0
QC1
IDT
™
/ ICS
™
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
1
ICS87931AYI-147 REV. A MARCH 29, 2007
ICS87931I-147
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 9, 17, 32
2
3
4
5
6
7
8, 16, 24,25
10, 11
12
13, 21, 28
14, 15
18
Name
nc
V
DDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
GND
CLK_EN0,
CLK_EN1
EXT_FB
V
DDO
QC0, QC1
PLL_SEL
Power
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Input
Pullup
Pullup
Pullup
Type
Unused
Description
No connect.
Analog supply pin.
Controls the frequency being fed to the output dividers.
LVCMOS / LVTTL interface levels.
Clock input. LVCMOS / LVTTL interface levels.
Active LOW Master reset. When logic LOW, the internal dividers are
reset causing the outputs to go low. When logic HIGH, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
19
20
22, 23
26, 27
29
30
31
CLK_SEL
EXTFB_SEL
QB1, QB0
QA1, QA0
DIV_SELA
DIV_SELB
DIV_SELC
Input
Input
Output
Output
Input
Input
Input
Pullup
Pullup/
Inver ting differential clock input. V
CC
/2 default when left floating.
Pulldown
Power supply ground.
Controls the enabling and disabling of the clock outputs. See Table 3B.
Pullup
LVCMOS / LVTTL interface levels.
External feedback. When LOW, selects internal feedback.
Pullup
When HIGH, selects EXT_FB. LVCMOS / LVTTL interface levels.
Output supply pins.
Bank C clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clocks as the input to the
Pullup
output dividers. When HIGH, selects PLL. When LOW, bypasses
the PLL. LVCMOS / LVTTL interface levels.
Clock select input. Selects the Phase Detector Reference.
Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Pulldown External feedback select. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank A clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 4A.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank B as described in Table 4A.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank C as described in Table 4A.
Pulldown
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
V
DDO,
V
DDO
= 3.465V
12
7
Maximum
Units
pF
kΩ
kΩ
pF
Ω
IDT
™
/ ICS
™
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
2
ICS87931AYI-147 REV. A MARCH 29, 2007
ICS87931I-147
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
Control Pin
CLK_SEL
PLL_SEL
EXTFB_SEL
POWER_DN
nMR
DIV_SELA:DIV_SELC
Logic 0
CLK0, nCLK0
Bypass PLL
Internal Feedback
VCO/1
Master Reset/Output Hi Z
QA(÷2); QB(÷2); QC(÷4)
Function
Logic 1
CLK1
PLL Enabled
EXT_FB
VCO/2
Enable Outputs
QA(÷4); QB(÷4); QC(÷6)
T
ABLE
3B. CLK_EN
X
F
UNCTION
T
ABLE
Inputs
CLK_EN1
0
0
1
1
CLK_EN0
0
1
0
1
DIV_SELA:DIVSELC
QAx
Toggle
LOW
Toggle
Toggle
QBx
LOW
LOW
LOW
Toggle
QCx
LOW
Toggle
Toggle
Toggle
T
ABLE
4A. VCO F
REQUENCY
F
UNCTION
T
ABLE
Inputs
DIV_
SELA
0
0
0
0
1
1
1
1
DIV_
SELB
0
0
1
1
0
0
1
1
DIV_
SELC
0
1
0
1
0
1
0
1
QAx
POWER_DN = 0
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/2
VCO/2
VCO/4
VCO/4
VCO/2
VCO/2
VCO/4
VCO/4
Outputs
QBx
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/6
VCO/4
VCO/6
VCO/4
VCO/6
VCO/4
VCO/6
QCx
POWER_DN = 1
VCO/8
VCO/12
VCO/8
VCO/12
VCO/8
VCO/12
VCO/8
VCO/12
POWER_DN = 1 POWER_DN = 0
POWER_DN = 1 POWER_DN = 0
T
ABLE
4B. I
NPUT
R
EFERENCE
F
REQUENCY TO
O
UTPUT
F
REQUENCY
F
UNCTION
T
ABLE
(I
NTERNAL
F
EEDBACK
O
NLY
)
Inputs
DIV_
SELA
0
0
0
0
1
1
1
1
DIV_
SELB
0
0
1
1
0
0
1
1
DIV_
SELC
0
1
0
1
0
1
0
1
QAx
POWER_DN = 0
4x
4x
4x
4x
2x
2x
2x
2x
2x
2x
2x
2x
x
x
x
x
4x
4x
2x
2x
4x
4x
2x
2x
Outputs
QBx
2x
2x
x
x
2x
2x
x
x
2x
4/3x
2x
4/3x
2x
4/3x
2x
4/3x
QCx
POWER_DN = 1
x
2/3x
x
2/3x
x
2/3x
x
2/3x
POWER_DN = 1 POWER_DN = 0
POWER_DN = 1 POWER_DN = 0
IDT
™
/ ICS
™
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
3
ICS87931AYI-147 REV. A MARCH 29, 2007
ICS87931I-147
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
VCO
VCO/2
POWER_DN
QA(÷2)
QB(÷4)
QC(÷6)
F
IGURE
1A. POWER_DN T
IMING
D
IAGRAM
QA
QB
QC
CLK_EN0
CLK_EN1
QA(÷2)
QB(÷4)
QC(÷6)
CLK_EN0
CLK_EN1
F
IGURE
1B. CLK_EN
X
T
IMING
D
IAGRAMS
IDT
™
/ ICS
™
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
4
ICS87931AYI-147 REV. A MARCH 29, 2007
ICS87931I-147
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DDA
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
65.7°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DDA
V
DDO
I
DDA
I
DDO
Parameter
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
20
100
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
5B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Input
High Voltage
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL,
CLK1, EXT_FB
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL
CLK1, EXT_FB
I
OH
= -20mA
I
OL
= 20mA
Test Conditions
Minimum Typical
Maximum
Units
V
IH
2
V
DDO
+ 0.3
V
V
IL
Input
Low Voltage
Input Current
-0.3
-0.3
2.4
0.8
1.3
±120
0.5
V
V
µA
V
V
I
IN
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, 3.3V Output Load Test Circuit.
T
ABLE
5C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IN
V
PP
Parameter
Input Current
Test Conditions
Minimum
Typical
Maximum
±120
1.3
V
DDO
- 0.85
Units
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
GND + 0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK0, nCLK0 is V
DDO
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
IDT
™
/ ICS
™
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
5
ICS87931AYI-147 REV. A MARCH 29, 2007
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