16Mx64 bits
PC100 SDRAM SO DIMM
based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V16M656BTU6 Series
DESCRIPTION
The HYM72V16M656BTU6 Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 16Mx16bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy
printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The HYM72V16M656BTU6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes mem-
ory. The HYM72V16M656BTU6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
•
•
•
•
PC100MHz support
144pin SDRAM Micro SO DIMM
Serial Presence Detect with EEPROM
1.18” (30.00mm) Height PCB with double sided com-
ponents
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
•
•
All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
•
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
•
•
•
SDRAM internal banks : four banks
Module bank : one physical bank
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM72V16M656TU6-8
HYM72V16M656TU6-P
HYM72V16M656TU6-S
HYM72V16M656TU6-8
HYM72V16M656TU6-P
HYM72V16M656TU6-S
Clock
Frequency
125MHz
100MHz
100MHz
125MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
Normal
4 Banks
4K
Low Power
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.1/Apr. 02
1
PC100 SDRAM SO DIMM
HYM72V16M656BTU6
PIN DESCRIPTION
PIN
CK0, CK1
CKE0
/S0
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
V
SS
SCL
SDA
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Ground
Serial Presence Detect Clock input
Serial Presence Detect Data input/output
No connection
Series
Rev. 0.1/Apr. 01
2
PC100 SDRAM SO DIMM
HYM72V16M656BTU6
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Series
BACK SIDE
PIN NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
FRONT SIDE
PIN NO.
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
BACK SIDE
PIN NO.
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
NAME
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
NC
NC
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
NC
NC
NAME
NC
NC
VSS
NC
NC
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10/AP
VCC
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
NAME
NC
*CK1
VSS
NC
NC
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
Voltage Key
61
63
65
67
69
CK0
VCC
/RAS
/WE
/S0
62
64
66
68
70
CKE0
VCC
/CAS
NC
NC
135
137
139
141
143
Note : * CK1 are connected with termination R/C (Refer to the Block Diagram)
Rev. 0.1/Apr. 01
3
PC100 SDRAM SO DIMM
HYM72V16M656BTU6
BLOCK DIAGRAM
Series
Note : 1. The serial resistor values of DQs are 10ohms
2. The padding capacitance of termination R/C for CK1 is 10pF
Rev. 0.1/Apr. 01
4
PC100 SDRAM SO DIMM
HYM72V16M656BTU6
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36
~61
BYTE62
BYTE63
BYTE64
BYTE65
~71
FUNCTION
DESCRIPTION
# of Bytes Written into Serial Memory at Module Manu-
facturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @/CAS Latency=3
Access Time from Clock @/CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random Column
Address
Burst Lenth Supported
# of Banks on Each SDRAM Device
SDRAM Device Attributes, /CAS Lataency
SDRAM Device Attributes, /CS Lataency
SDRAM Device Attributes, /WE Lataency
SDRAM Module Attributes
SDRAM Device Attributes, General
SDRAM Cycle Time @/CAS Latency=2
Access Time from Clock @/CAS Latency=2
SDRAM Cycle Time @/CAS Latency=1
Access Time from Clock @/CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse Width (tRAS)
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
Data Signal Input Hold Time
Superset Information (may be used in future)
SPD Revision
Checksum for Byte 0~62
Manufacturer JEDEC ID Code
....Manufacturer JEDEC ID Code
2ns
1ns
2ns
1ns
8ns
6ns
FUNCTION
-8
-P
128 Bytes
256 Bytes
SDRAM
13
9
1 Bank
64 Bits
-
LVTTL
10ns
6ns
None
7.8125us
/ Self Refresh Supported
x16
None
tCCD = 1 CLK
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
-
-
-
-
20ns
16ns
20ns
48ns
10ns
6ns
-
-
20ns
20ns
20ns
50ns
128MB
2ns
1ns
2ns
1ns
-
Intel SPD 1.2B
-
Hynix JEDED ID
Unused
Hynix (Korea Area)
HSA (United States Area)
HSU (Europe Area)
HSJ (Japan Area)
HSS(Singapore)
ASIA Area
h
2ns
1ns
2ns
1ns
20h
10h
20h
10h
12ns
6ns
-
-
20ns
20ns
20ns
50ns
00h
00h
00h
00h
14h
10h
14h
30h
10ns
6ns
-S
-8
80h
08h
04h
0Dh
09h
01h
40h
00h
01h
80h
60h
A0h
60h
00h
82h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h
60h
00h
00h
14h
14h
14h
32h
20h
20h
10h
20h
10h
00h
12h
h
ADh
FFh
0*h
1*h
2*h
3*h
4*h
5*h
h
3, 8
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
2
VALUE
-P
80h
08h
04h
0Dh
09h
01h
40h
00h
01h
A0h
60h
1
-S
NOTE
Series
BYTE72
Manufacturing Location
9
Rev. 0.1/Apr. 01
5
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