Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
The MH2V645CZJJ is 2097152 - word by 64 - bit dynamic
RAM module. This consists of eight industry standard 2Mx8
dynamic RAMs in TSOP and one industry EEPROM in TSSOP.
The mounting of TSOP on a card edge dual in line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module,suitable for easy
interchange of addition of modules.
APPLICATION
Main memory unit for computer,Microcomputer
memory,Refresh memory for CRT.
FEATURES
RAS
CAS Address
OE
Power
access access access access Cycle dissipation
time
time
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
MH2V645CZJJ-5,5S
MH2V645CZJJ-6,6S
MH2V645CZJJ-7,7S
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
3480
2880
2520
single 3.3V ± 0.3V supply
Low stand-by power dissipation
14.4mW- - - - - - - - - CMOS input level
5.76mW- - - - - - - - - CMOS input level*
operating power dissipation
MH2V645CZJJ-5,5S - - - - 4200 mW(max.)
MH2V645CZJJ-6,6S - - - - 3480 mW(max.)
MH2V645CZJJ-7,7S - - - - 3040 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output TTL compatible and low capacitance
2048 refresh cycle every 32.0ms(A0~A10)
Utilizes industry standard 2Mx8 RAMs in TSOP and
industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx8)
Hyper page mode , Read-modify-write,RAS-only
refresh,CAS before RAS refresh,Hidden refresh
capabilities.
Early-write mode,OE and W to control output buffer
impedance.
*:Applicable to self refresh version(MH2V645CZJJ-5S,-6S,-7S)
only
SPD Table
Byte No.
0
MH2V645CZJJ-5
MH2V645CZJJ-5S
MH2V645CZJJ-6
MH2V645CZJJ-6S
MH2V645CZJJ-7
MH2V645CZJJ-7S
MIT-DS-0034-1.0
1
2
3
4
5
6
7
8
9
32
10 11 12 13 14 27 28 29 30 31
00 1E 00 12 32
00 1E 00 12 32
00 28 00 14 3C
00 28 00 14 3C
00 32 00 14 46
00 32
00 14 46
04
04
04
04
04
04
80 08 02 0B 0A 01 40 00 01
0D 00 00 08
80 08 02 0B 0A 01 40 00 01 32 0D 00 80 08
80 08 02 0B 0A 01 40 00 01 3C 0F 00 00 08
80 08 02 0B 0A 01 40 00 01
80 08 02 0B 0A 01 40 00 01
3C 0F
14
14
46
80 08 02 0B 0A 01 40 00 01 46
00 80 08
00 00 08
00 80 08
MITSUBISHI
ELECTRIC
( 1 / 25 )
Jan/23/1997
Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
PIN CONFIGURATION
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
/CAS0
/CAS1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
Reserved
Reserved
RFU
Vcc
RFU
/WE
/RAS0
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
/CAS4
/CAS5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
Reserved
Reserved
FRU
Vcc
RFU
RFU
RFU
RFU
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
/OE
Vss
Reserved
Reserved
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
/CAS2
/CAS3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
RFU
Vss
Reserved
Reserved
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
NC
Vss
NC
NC
Vcc
/CAS6
/CAS7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
NC,RFU,Reserved: NO CONNECTION
RFU:Reserved Future Use
MIT-DS-0034-1.0
MITSUBISHI
ELECTRIC
( 2 / 25 )
Jan/23/1997
Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Block Diagram
A0~A10
/OE
/WE
/RAS0
/CAS0
/CAS /RAS /WE /OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/CAS1
/CAS /RAS /WE /OE
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CAS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/CAS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/CAS /RAS /WE /OE
I/O0
I/O1
I/O2
I/O3
D3
I/O4
I/O5
I/O6
I/O7
/CAS /RAS /WE /OE
I/O0
I/O1
I/O2
I/O3
D2
I/O4
D2
I/O5
I/O6
I/O7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/CAS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/CAS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/CAS /RAS /WE /OE
I/O0
I/O1
I/O2
I/O3
D7
I/O4
I/O5
I/O6
I/O6
I/O7
SERIAL PD
Vcc
C1~C8
/CAS4
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
/CAS5
/CAS /RAS /WE /OE
I/O0
I/O0
I/O1
I/O1
I/O2
I/O2
I/O3
I/O3
D5
D5
I/O4
I/O4
I/O5
I/O5
I/O6
I/O6
I/O7
I/O7
/CAS /RAS /WE /OE
I/O0
I/O0
I/O1
I/O1
I/O2
I/O2
I/O3
I/O3
D4
I/O4
I/O4
I/O5
I/O5
I/O6
I/O6
I/O7
I/O7
D0
D1
D1
/CAS /RAS /WE /OE
I/O0
I/O1
I/O2
I/O3
D6
I/O4
I/O5
I/O6
I/O7
D0 to D7
D0 to D7
SCL
A0 A1 A2
SDA
Vss
Vss
MIT-DS-0034-1.0
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ELECTRIC
( 3 / 25 )
Jan/23/1997
Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
a number of other functions, e.g., Hyper page mode,
/RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
FUNCTION
The MH2V645CZJJ provide, in addition to normal
read, write, and read-modify-write operations,
Table 1 Input conditions for each mode
Inputs
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
/RAS-only refresh
Hidden refresh
/CAS before /RAS refresh
Standby
Self refresh
/RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
/CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
ACT
/W
NAC
ACT
ACT
ACT
DNC
NAC
NAC
DNC
NAC
Input/Output
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
Refresh
YES
YES
YES
YES
YES
YES
YES
NO
YES
Remark
Hyper
page mode
identical
Row Column
/OE address address Input
ACT
APD
APD
OPN
DNC
APD
APD
VLD
DNC
APD
APD
VLD
ACT
APD
APD
VLD
DNC
APD
DNC
DNC
ACT
APD
DNC
OPN
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
*
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
*MH2V645CZJJ-5S,-6S,-7S only
MIT-DS-0034-1.0
MITSUBISHI
ELECTRIC
( 4 / 25 )
Jan/23/1997
Preliminary
Some of contents are subject
to change without notice.
MITSUBISHI LSIs
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Conditions
With respect to Vss
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature (SOJ)
Ratings
-0.5~4.6
-0.5~4.6
-0.5~4.6
50
8
0~ 70
-40~ 100
Unit
V
V
V
mA
W
°C
°C
Ta=25°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
(Ta=0~ 70°C, unless otherwise noted) (Note 1)
Min
3.0
0
2.0
**-0.3
Limits
Nom
3.3
0
Max
3.6
0
Vcc+0.3
0.8
Unit
V
V
V
V
Note 1 : All voltage values are with respect to Vss
** : VIL(Min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss)
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
II
Parameter
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V≤VOUT≤3.6V
0V≤VIN≤3.6V, Other input pins=0V
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS≥Vcc -0.2, output open
/RAS cycling, /CAS= VIH
tRC=min.
output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
/CAS before /RAS refresh cycling
tRC=min.
output open
/RAS=/CAS≤0.2V
output open
High-level output voltage
Low-level output voltage
Off-state output current
Input current
-5,-5S
Average supply
-6,-6S
ICC1 (AV) current
from Vcc operating (Note 3,4,5) -7,-7S
ICC2
Supply current from Vcc , stand-by
Min
2.4
0
-10
-80
-5,-5S
Average supply
ICC3 (AV) current
-6,-6S
from Vcc refreshing (Note 3,5) -7,-7S
Average supply current
-5,-5S
-6,-6S
ICC4(AV) from Vcc
Hyper-Page-Mode (Note 3,4,5) -7,-7S
Average supply current
-5,-5S
from Vcc
-6,-6S
ICC6(AV)
/CAS before /RAS refresh
(Note 3,5) -7,-7S
mode
Average supply current
Limits
Typ Max
Vcc
0.4
10
80
1160
960
840
16
4
1160
960
840
1120
920
720
1160
960
840
1600
Unit
V
V
uA
uA
mA
mA
mA
mA
mA
uA
ICC9(AV)*
from Vcc Self-Refresh mode
(Note 6)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VOH
CAPACITANCE
Symbol
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
Parameter
Test conditions
VI=Vss
f=1MHZ
Vi=25mVrms
Min
CI (A)
Input capacitance, address inputs
Input capacitance, clock inputs except CAS
CI
C(CAS) Input capacitance, CAS
C(DQ) Input/Output capacitance,DATA
Limits
Typ Max
55
65
25
25
Unit
pF
pF
pF
pF
MIT-DS-0034-1.0
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ELECTRIC
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Jan/23/1997