Preliminary Data Sheet
64Mbit – High Speed SDRAM (150 MHz)
8Mx8, 4Mx16 HSDRAM
Description
The Enhanced Memory Systems SM3603 and SM3604 High-
Speed SDRAM (HSDRAM) devices are high performance
versions of the proposed JEDEC PC-133 SDRAM. While
compatible with standard SDRAM, they provide the faster
clock access time (4.5 ns), shorter random access latency
(31.2 ns), and fast bank cycle time (53.3 ns) needed to
improve system stability, capacity, and performance in
systems operating at 150 MHz bus speed. The HSDRAM is
ideal for any high performance system including PCs,
workstations, servers, communications switches, DSP
systems, 3-D graphics, and embedded computers.
Features
•
•
•
JEDEC Standard PC-133 SDRAM
Fast 4.5 ns Clock Access Time
Low Latency Operation (3:2:2 @ 150 MHz)
•
CAS Latency = 3
•
RAS to CAS Delay = 2
•
Precharge Delay = 2
Fast Random Access Time (31.2 ns)
Fast Random Cycle time (53.3 ns)
Programmable Burst length (1, 2, 4, 8, full page)
Programmable CAS Latency (2, 3)
Low Power suspend, Self Refresh, and Power
Down Modes Supported
4K Refresh / 64 ms
Single 3.3V
±
0.3V Power Supply
54-pin TSOP-II (0.8mm pin pitch)
•
•
•
•
•
•
•
•
Block Diagram (4Mx16 shown)
ADDRESS BUFFERS
ROW DECODER
BA1
BA0
A(11:0)
BANK A
4K rows x
256 col x
16 bits
BANK B
4K rows x
256 col x
16 bits
BANK C
4K rows x
256 col x
16 bits
BANK D
4K rows x
256 col x
16 bits
SENSE AMPLIFIERS
COLUMN DECODER
SENSE AMPLIFIERS
COLUMN DECODER
SENSE AMPLIFIERS
COLUMN DECODER
SENSE AMPLIFIERS
COLUMN DECODER
Data I/O Buffers
CLK
CKE
/CS
/RAS
/CAS
/WE
UDQM,
LDQM
DQ(15:0)
COMMAND
DECODER
and
TIMING
GENERATOR
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 1 of 9
64Mbit – High Speed SDRAM (150 MHz)
8Mx8, 4Mx16 HSDRAM
Pin Assignments (Top View)
Preliminary Data Sheet
8Mx8
4Mx16
VDD
DQ0
VDD
NC
DQ1
VSS
NC
DQ2
VDD
NC
DQ3
VSS
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A0
A1
A2
A3
VDD
VDD
DQ0
VDD
DQ1
DQ2
VSS
DQ3
DQ4
VDD
DQ5
DQ6
VSS
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSS
DQ14
DQ13
VDD
DQ12
DQ11
VSS
DQ10
DQ9
VDD
DQ8
VSS
NC
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSS
NC
DQ6
VDD
NC
DQ5
VSS
NC
DQ4
VDD
NC
VSS
NC
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
54 PIN TSOP-II
400 x 875 mils
0.8 mm pitch
UDQM DQM
A10/AP A10/AP
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 2 of 9
Revision 1.0
Preliminary Data Sheet
64Mbit – High Speed SDRAM (150 MHz)
8Mx8, 4Mx16 HSDRAM
Pin Descriptions
Symbol
CLK
CKE
Type
Input
Input
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CLK.
Clock Enable: CKE activate (high) or deactivate (low) the CLK signals. Deactivating the
clock initiates the Power-Down and Self-Refresh operations (all banks idle), or Clock
Suspend operation. CKE is synchronous until the device enters Power-Down and Self-
Refresh modes where it is asynchronous until the mode is exited.
Chip Select: CS# enables (low) or disables (high) the command decoder. When the
command decoder is disabled, new commands are ignored but previous operations
continue.
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command
to be executed.
Bank Addresses: These inputs define to which of the 4 banks a given command is being
applied.
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-
A8 define the column address during Read and Write commands. A10/AP invokes the
Auto-precharge operation. During manual Precharge commands, A10/AP low specifies a
single bank precharge while A10/AP high precharges all banks. The address inputs are
also used to program the Mode Register.
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these
pins and must be set-up and held relative to the rising edge of clock. For Read cycles, the
device drives output data on these pins after the CAS latency is satisfied.
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and acts as a
synchronous output enable (2-cycle latency) for read data.
Power Supply: +3.3 V
Ground
No connect - open pin.
CS#
Input
RAS#, CAS#,
WE#
BA1, BA0
(A12, A13)
A0-A11
Input
Input
Input
DQ0-DQ15
Input/
Output
DQM,
UDQM,
LDQM
V
DD
V
SS
NC
Input
Supply
Supply
-
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 3 of 9
64Mbit – High Speed SDRAM (150 MHz)
8Mx8, 4Mx16 HSDRAM
Electrical Characteristics
Absolute Maximum Ratings
Description
Power Supply Voltage
Voltage on any Pin with Respect to Ground
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
DC Output Current (I/O pins)
Symbol
V
DD
V
IN
, V
OUT
T
A
T
stg
P
D
I
OUT
Preliminary Data Sheet
Value
-1V to +4.6V
-0.5V to +4.6V
0°C to +70°C
-55°C to +125°C
TBD
50mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only, and the functional operation of the device at these, or any other conditions above those listed in the
operational section of the specification, is not implied. Exposure to conditions at absolute maximum ratings for extended
periods may affect device reliability.
DC Operating Conditions (T
A
= 0°C to 70°C)
Symbol
V
DD
V
IH
V
IL
I
I(L)
I
O(L)
V
OH
V
OL
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= +4mA)
Parameter
Min
3.0
2.0
-0.3
-
-
2.4
0.0
Typical
3.3
3.3
0.0
-
-
-
-
Max
3.6
V
DD
+ 0.3
0.8
±1
±1
V
DD
0.4
Units
V
V
V
µA
µA
V
V
Notes
Capacitance (T
A
= 25°C, f = 1MHz, VDD = 3.3V
±0.3V,
not 100% tested)
Symbol
C
In1
C
In2
C
I/O
Parameter
Input Capacitance (BA1, BA0, A0-11)
Input Capacitance (all control inputs)
I/O Capacitance (DQ0-15)
Min
2.5
2.5
3.5
Typical
3.3
3.3
4.5
Max
4.0
4.0
5.5
Units
pF
pF
pF
Notes
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 4 of 9
Revision 1.0
Preliminary Data Sheet
64Mbit – High Speed SDRAM (150 MHz)
8Mx8, 4Mx16 HSDRAM
AC Characteristics (T
A
= 0°C to 70°C)
1. An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by
a minimum of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the V
TT
= 1.4V crossover point.
t
T
Clock
t
SETUP
Input
t
AC
t
LZ
Output
t
OH
V
TT
VIH
VTT
VIL
V
TT
R
T
= 50 ohm
Z
0
= 50 ohm
Output
C
LOAD
= 30pF
t
HOLD
AC Output Load Circuit
3. The transition time is measured between V
IH
and V
IL
(or between V
IH
and V
IL
).
4. AC measurements assume t
T
= 1ns.
5. In addition to meeting the transition rate specification, the clock and CKE must transition V
IH
and V
IL
(or between V
IH
and V
IL
) in a monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 5 of 9
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