2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Features
DDR3 SDRAM UDIMM
MT18JSF25672AY – 2GB
MT18JSF51272AY – 4GB
Features
•
DDR3 functionality and operations supported as
defined in the component data sheet
•
240-pin, unbuffered dual in-line memory module
(UDIMM)
•
Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
•
2GB (256 Meg x 72), 4GB (512 Meg x 72)
•
V
DD
= 1.5V ±0.075V
•
V
DDSPD
= +3.0V to +3.6V
•
Supports ECC error detection and correction
•
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
•
Dual rank
•
On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
•
8 internal device banks
•
Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
•
Selectable BC4 or BL8 on-the-fly (OTF)
•
Gold edge contacts
•
Lead-free
•
Fly-by topology
•
Terminated control, command, and address bus
Table 1: Key Timing Parameters
Speed
Grade
-1G6
-1G4
-1G1
-1G0
-80B
Industry
Nomenclature
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
Data Rate (MT/s)
CL = 11 CL = 10
1600
–
–
–
–
1333
1333
–
–
–
CL = 9
1333
1333
–
–
–
CL = 8
1066
1066
1066
1066
–
CL = 7
1066
1066
1066
–
–
CL = 6
800
800
800
800
800
CL = 5
667
667
667
667
667
t
RCD
t
RP
t
RC
Figure 1: 240-Pin UDIMM (MO-269 R/C E)
Module height: 30mm (1.18in)
Options
•
Operating
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
•
Package
–
240-pin DIMM (lead-free)
•
Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
2
–
2.5ns @ CL = 5 (DDR3-800)
2
–
2.5ns @ CL = 6 (DDR3-800)
2
Notes:
temperature
1
Marking
None
I
Y
-1G6
-1G4
-1G1
-1G0
-80C
-80B
1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
(ns)
13.125
13.125
13.125
15
15
(ns)
13.125
13.125
13.125
15
15
(ns)
48.125
49.125
50.625
52.5
52.5
PDF: 09005aef83014429
jsf18c256_512x72a.pdf - Rev. E 2/11 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
2GB
8K
16K A[13:0]
8 BA[2:0]
1Gb 128 Meg x 8
1K A[9:0]
2 S#[1:0]
4GB
8K
32K A[14:0]
8 BA[2:0]
2Gb 256 Meg x 8
1K A[9:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
2
Part Number
Density
Configuration
MT18JSF25672A(I)Y-1G6__
MT18JSF25672A(I)Y-1G4__
MT18JSF25672A(I)Y-1G1__
MT18JSF25672A(I)Y-1G0__
MT18JSF25672A(I)Y-80C__
MT18JSF25672A(I)Y-80B__
2GB
2GB
2GB
2GB
2GB
2GB
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
8-8-8
5-5-5
6-6-6
Table 4: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Module
2
Part Number
Density
Configuration
MT18JSF51272A(I)Y-1G6__
MT18JSF51272A(I)Y-1G4__
MT18JSF51272A(I)Y-1G1__
MT18JSF51272A(I)Y-1G0__
MT18JSF51272A(I)Y-80C__
MT18JSF51272A(I)Y-80B__
Notes:
4GB
4GB
4GB
4GB
4GB
4GB
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
8-8-8
5-5-5
6-6-6
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT18JSF25672AY-1G1D1.
PDF: 09005aef83014429
jsf18c256_512x72a.pdf - Rev. E 2/11 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Pin Assignments
Pin Assignments
Table 5: Pin Assignments
240-Pin DDR3 UDIMM Front
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
NC
CKE0
V
DD
BA2
NC
V
DD
A11
A7
V
DD
A5
A4
V
DD
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
A2
V
DD
CK1
CK1#
V
DD
V
DD
V
REFCA
NC
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
S1#
ODT1
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23#
V
SS
DQ28
DQ29
240-Pin DDR3 UDIMM Back
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
NC
RESET#
CKE1
V
DD
A15
A14
V
DD
NF/A14
1
A9
V
DD
A8
A6
V
DD
A3
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Symbol
A1
V
DD
V
DD
CK0
CK0#
V
DD
EVENT#
A0
V
DD
BA1
V
DD
RAS#
S0#
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
Note:
1. Pin 172 is NF for 2GB or A14 for 4GB.
PDF: 09005aef83014429
jsf18c256_512x72a.pdf - Rev. E 2/11 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
Clock:
Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Data mask (x8 devices only):
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination:
Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-
ized as though a normal power-up was executed.
Chip select:
Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
Used to configure the temperature sensor/SPD EEPROM ad-
dress range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
Used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM on the I
2
C bus.
Check bits:
Used for system error detection and correction.
Data input/output:
Bidirectional data bus.
Data strobe:
Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
BAx
Input
CKx,
CKx#
CKEx
DMx
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
Input
Input
Input
(LVCMOS)
Input
Input
Input
I/O
I/O
I/O
Sx#
SAx
SCL
CBx
DQx
DQSx,
DQSx#
PDF: 09005aef83014429
jsf18c256_512x72a.pdf - Rev. E 2/11 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Pin Descriptions
Table 6: Pin Descriptions (Continued)
Symbol
SDA
TDQSx,
TDQSx#
Type
I/O
Output
Description
Serial data:
Used to transfer addresses and data into and out of the temperature sensor/
SPD EEPROM on the I
2
C bus.
Redundant data strobe (x8 devices only):
TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
EVENT#
V
DD
V
DDSPD
V
REFCA
V
REFDQ
V
SS
V
TT
NC
NF
Output
Parity error output:
Parity error found on the command and address bus.
(open drain)
Output
Temperature event:The
EVENT# pin is asserted by the temperature sensor when crit-
(open drain) ical temperature thresholds have been exceeded.
Supply
Supply
Supply
Supply
Supply
Supply
–
–
Power supply:
1.5V ±0.075V. The component V
DD
and V
DDQ
are connected to the mod-
ule V
DD
.
Temperature sensor/SPD EEPROM power supply:
3.0–3.6V.
Reference voltage:
Control, command, and address V
DD
/2.
Reference voltage:
DQ, DM V
DD
/2.
Ground.
Termination voltage:
Used for control, command, and address V
DD
/2.
No connect:
These pins are not connected on the module.
No function:
These pins are connected within the module, but provide no functionality.
PDF: 09005aef83014429
jsf18c256_512x72a.pdf - Rev. E 2/11 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
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