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MMDP-65698V-40

产品描述Standard SRAM, 64KX4, 40ns, CMOS, CDFP28,
产品类别存储    存储   
文件大小102KB,共9页
制造商TEMIC
官网地址http://www.temic.de/
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MMDP-65698V-40概述

Standard SRAM, 64KX4, 40ns, CMOS, CDFP28,

MMDP-65698V-40规格参数

参数名称属性值
是否Rohs认证不符合
Reach Compliance Codeunknown
最长访问时间40 ns
I/O 类型COMMON
JESD-30 代码R-XDFP-F28
JESD-609代码e0
内存密度262144 bit
内存集成电路类型STANDARD SRAM
内存宽度4
端子数量28
字数65536 words
字数代码64000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织64KX4
输出特性3-STATE
封装主体材料CERAMIC
封装代码DFP
封装等效代码FL28,.4
封装形状RECTANGULAR
封装形式FLATPACK
并行/串行PARALLEL
电源5 V
认证状态Not Qualified
最大待机电流0.00008 A
最小待机电流2 V
最大压摆率0.07 mA
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
Base Number Matches1

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MATRA MHS
M 65698
64 K
×
4 Ultimate CMOS SRAM
Introduction
The M 65698 is a very low power CMOS static RAM
organized as 65536
×
4 bits. It is manufactured using the
MHS high performance CMOS technology named
SCMOS.
With this process, MHS is the first to bring the solution for
applications where fast computing is as mandatory as low
consumption, such as aerospace electronics, portable
instruments or embarked systems.
Utilizing an array of six transistors (6T) memory cells, the
M 65698 combines an extremely low standby
supply current (Typical value = 0.1
µA)
with a fast access
time at 40 ns. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
Extra protection against heavy ions is given by the use of
an epitaxial layer of a P substrate.
The M 67698 is 100 % processed following the test
methods of MIL STD 883 and/or ESA/SCC 9000, making
it ideally suitable for military/space applications that
demand superior levels of performance and reliability.
Features
D
Access time
commercial : 35(*), 40, 45, 55 ns
industrial and military : 40(*), 45, 55 ns
D
Very low power consumption
active : 50 mW (typ)
standby : 0.5 W (typ)
data retention : 0.4 W (typ)
D
Wide temperature range : -55 to + 125
°C
(*) Preliminary. Consult sales.
D
D
D
D
D
D
300 mils width package
TTL compatible inputs and outputs
Asynchronous
Single 5 volt supply
Equal cycle and access time
Gated inputs :
no pull-up/down
resistors are required
Interface
Block Diagram
Rev. C (12/12/94)
1

 
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