FMD4A16LCx–30A(C)x
DDR Sync DRAM Features
•
Functionality
- Double-data-rate architecture ; two data transfers
per CLK cycle.
- Bidirectional data strobe per byte data (DQS).
- No DLL ; CLK to DQS is not Synchronized.
- Differential CLK inputs( CLK and /CLK ).
- Commands entered on each positive CLK edge.
- DQS edge-aligned with data for Reads;
center-aligned with data for Writes.
- Four internal banks for concurrent operation.
- Data masks (DM) for masking write data-one mask
per byte.
- Programmable burst lengths : 2, 4, 8, 16.
- Programmable CAS Latency : 2, 3.
- Concurrent auto pre-charge option is supported.
- Auto refresh and self refresh modes.
- LVCMOS-compatible inputs.
•
Low Power Features
- Low voltage power supply.
- Auto TCSR (Temperature Compensated Self Refresh).
- Partial Array Self Refresh power-saving mode.
- Deep Power Down Mode.
- Driver Strength Control.
•
Operating Temperature Ranges
- Commercial (0℃ to +70℃).
- Extended (-25℃ to +85℃).
- Industrial (-40℃ to +85℃).
•
Package
- 60-Ball FBGA ( 8 X 10 X 0.8mm )
•
Functional Description
The FMD4A16LCx Family is high-performance CMOS
Dynamic RAMs (DRAM) organized as 8M x 16. These
devices feature advanced circuit design to provide low
active current and extremely low standby current. The device
is compatible with the JEDEC standard Low Power DDR
SDRAM specifications.
•
Configuration
- 8 Meg X 16 (2 Meg X 16 X 4Bank ).
Logic Block Diagram
Refresh
/ CLK
CLK
CKE
/CS
/WE
/CAS
/RAS
Self
Refresh
Counter
Row
Pre_
Decoder
Row Active
Bank3
Bank2
Bank1
Bank0
2M x 16
Memory
Array
Column decoders
Sense amp
Input
Data
Controller
Logic
Row decoders
Row decoders
Row decoders
Row decoders
DM0 –
DM1
State Machine
Address Buffers
Column Active
Column
Pre_
Decoder
Data Strobe
Receiver
DQS0 –
DQS1
Data
Input
Register
DQ0 –
DQ15
Data
Output
Register
Bank Select
Column
Add
Counter
Burst
Length
CAS
Latency
Write Drivers
DM Mask
A0-A11
BA0, BA1
Address
Register
Mode Register
Data Out Control
Data Strobe
Transmitter
DQS0 –
DQS1
Selection Guide
Device
Voltage
[1]
V
DD
FMD4A16LCx-30Ax
FMD4A16LCx-30Cx
2.7-3.3V
2.3-2.7V
V
DDQ
2.7- V
DD
2.3-V
DD
Clock
Frequency
166MHz
83MHz
166MHz
83MHz
3
Access Time(t
AC
)
CL=2
6.0ns
5.5ns
6.0ns
CL=3
5.5ns
t
RCD
t
RP
18ns
18ns
18ns
18ns
18ns
18ns
18ns
18ns
Note :
1. See page #18 for operating range.
Rev. 0.2, Jan. ‘09
FMD4A16LCx–30A(C)x
General Description
The 128Mb Low Power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-bank DRAM. Each of the 33,554,432-bit banks is
organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb Low Power DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to
transfer four data words per clock cycle at the I/O balls. A single read or write access for the 128Mb DDR
SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core
and two corresponding
n-bit
wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the Low Power DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for
WRITEs. The x16 offering has two data strobes.
The 128Mb Low Power DDR SDRAM operates from a differential clock (CLK and /CLK); the crossing of CLK
going HIGH and /CLK going LOW will be referred to as the positive edge of CLK. Commands (address and
control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the Low Power DDR SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select
the bank and the starting column location for the burst access.
The Low Power DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,4,8 or 16. An
auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of Low Power DDR SDRAMs allows
for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
time.
An auto-refresh mode is provided, along with a power saving power-down mode. Self refresh mode offers
temperature compensation through an on-chip temperature sensor and partial array self refresh, which allow
users to achieve additional power saving. The temperature sensor is enabled by default and the partial array
self refresh can be programmed through the extended mode register.
Notes :
1. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is
divided into two bytes. For the first byte (DQ0–DQ7) DM refers to DM0 and DQS refers to DQS0. For the
second byte (DQ8–DQ15) DM refers to DM1 and DQS refers to DQS1.
2. Complete functionality is described throughout the document and any page or diagram may have been
simplified to convey a topic and may not be inclusive of all requirements.
3. Any specific requirement takes precedence over a general statement.
Rev. 0.2, Jan. ‘09
5
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