N-Channel JFET
Monolithic Dual
CORPORATION
SST404 / SST405 / SST406
FEATURES
DESCRIPTION
The SST404 Series is a very Low Noise Monolithic
N-Channel JFET Pair in a surface mount SO-8 plastic
package. Designed utilizing Calogic’s proprietary JFET
processing techniques these devices are ideal for front end
amplification of low level signals. The low noise, low leakage
and good frequency response are excellent features for
sensitive medical, instrumentation and infrared designs.
ORDERING INFORMATION
Part
SST404-6
Package
Plastic SO-8
Temperature Range
-55
o
C to +125
o
C
•
Very Low Noise . . . . . . . . . . . . . e
n
< 10 nV/ Hz @ 10Hz
......
I
•
Low Input Bias . .Voltage.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. B
G
< 2pA
V
> 50V
•
High Breakdown
•
Precision Instrumentation
•
Input Amplifiers
•
Impedance Converters
APPLICATIONS
NOTE: For Sorted Chips in Carriers, See U401 Series
PIN CONFIGURATIONS
SO-8
TOP VIEW
(1) S1
(2) D1
(3) G1
(4) N/C
N/C (8)
G2 (7)
D2 (6)
S2 (5)
CJ2
PRODUCT MARKING
SST404
SST405
SST406
R04
R05
R06
SST404 / SST405 / SST406
CORPORATION
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25
o
C unless otherwise noted)
Parameter/Test Condition
Gate-Drain Voltage
Gate-Source Voltage
Forward Gate Current
Power Dissipation (per side)
(total)
Power Derating
(per side)
(total)
Operating Junction Temperature
Storage Temperature
Lead Temperature (1/16" from case for 10 seconds)
Symbol
V
GD
V
GS
I
G
P
D
Limit
-50
-50
10
300
500
2.4
4
-55 to 150
-55 to 200
300
Unit
V
V
mA
mW
mW
mW/
o
C
mW/
o
C
o
C
o
C
o
C
T
J
T
stg
T
L
ELECTRICAL CHARACTERISTICS
(T
A
= 25
o
C unless otherwise noted)
SYMBOL
STATIC
V
(BR)GSS
V
(BR)G1 - G2
V
GS(OFF
)
I
DSS
I
GSS
Gate-Source Breakdown Voltage
Gate-Gate Breakdown Voltage
Gate-Source Cut off Voltage
Saturation Drain Current
2
Gate Reverse Current
-58
-58
-1.5
3.5
-2
-1
Gate Operating Current
Drain-Source On-Resistance
Gate-Source Voltage
Gate-Source Forward Voltage
-2
-0.8
r
DS(ON)
V
GS
V
GS(F)
DYNAMIC
g
fs
g
os
g
fs
g
os
C
iss
C
rss
e
n
MATCHING
| V
GS1
- V
GS2
| Differential Gate-Source Voltage
∆
| V
GS1
- V
GS2
| Gate-Source Voltage Differential Change with
Temperature
∆T
CMRR
Common Mode Rejection Ratio
102
95
15
25
25
90
20
40
40
40
80
80
mV
o
CHARACTERISTCS
TYP
1
SST404
SST405
SST406
UNIT
TEST CONDITIONS
MIN MAX MIN MAX MIN MAX
-50
±50
-50
±50
-50
±50
V
I
G
= -1µA, V
DS
= 0V
I
G
=
±1µA,
V
DS
= 0V, V
GS
= 0V
V
DS
= 15V, I
D
= 1nA
mA
pA
nA
V
DS
= 15V, V
GS
= 0V
V
GS
= -30V, V
DS
= 0V
T
A
= 125
o
C
V
DG
= 15V, I
D
= 200µA
T
A
= 125
o
C
V
GS
= 0V, I
D
= 0.1mA
V
DG
= 15V, I
D
= 200µA
IG = 1mA, V
DS
= 0V
-0.5 -2.5 -0.5 -2.5 -0.5 -2.5
0.5
10
-25
0.5
10
-25
0.5
10
-25
I
G
-15
-10
-15
-10
-15
-10
pA
nA
Ω
250
-1
0.7
-2.3
-2.3
-2.3
V
Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance
Equivalent Input Noise Voltage
1.5
1.3
1.5
10
1
2
2
1
2
2
1
2
2
mS
µS
VDG = 15V, I
D
= 200µA
f = 1kHz
VDS = 10V, V
GS
= 0V
f = 1kHz
2
7
20
8
2
7
20
8
3
20
2
7
20
8
3
20 nV/ Hz
pF
1.5
10
3
20
V
DG
= 15V, I
D
= 200µA
f = 1MHz
V
DG
= 15V, I
D
= 200µA
f = 10Hz
V
DG
= 10V, I
D
= 200µA
T
A
= -55 to 25
o
C V
DG
= 10V,
µV/
C
T
A
= 25 to 125
o
C I
D
= 200µA
dB
V
DG
= 10 to 20V, I
D
= 200µA
NOTES: 1. For design aid only, not subject to production testing.
2. Pulse test; PW = 300µs, duty cycle
≤
3%.
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