N-Channel JFET Switch
CORPORATION
J108 – J110 / SST108 – SST110
FEATURES
Low Cost
Automated Insertion Package
Low Insertion Loss
No Offset or Error Voltages Generated by Closed Switch
Purely Resistive
High Isolation Resistance from Driver
Fast Switching
Low Noise
•
•
•
•
•
•
APPLICATIONS
Analog Switches
Choppers
Commutators
Low-Noise Audio Amplifiers
•
•
•
•
PIN CONFIGURATION
SOT-23
G
TO-92
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25
o
C unless otherwise specified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature Range . . . . . . . . . . . . . -55
o
C to +150
o
C
Operating Temperature Range . . . . . . . . . . . -55
o
C to +135
o
C
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300
o
C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/
o
C
NOTE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
D
S
G
D S
5018
PRODUCT MARKING (SOT-23)
SST108
I
08
SST109
I
09
SST110
I
10
ORDERING INFORMATION
Part
Package
J108-110
Plastic TO-92
XJ108-110
Sorted Chips in Carriers
SST109-110 Plastic SOT-23
Temperature Range
-55
o
C to +135
o
C
-55
o
C to +135
o
C
-55
o
C to +135
o
C
ELECTRICAL CHARACTERISTICS
(T
A
= 25
o
C unless otherwise specified)
SYMBOL
I
GSS
V
GS(off)
BV
GSS
I
DSS
I
D(off)
r
DS(on)
C
dg(off)
C
sg(off)
C
dg(on)
+ C
sg(on)
t
d(on)
t
r
t
d(off)
t
f
PARAMETER
Gate Reverse Current (Note 1)
Gate-Source Cutoff Voltage
Gate-Source Breakdown Voltage
Drain Saturation Current (Note 2)
Drain Cutoff Current (Note 1)
Drain-Source ON Resistance
Drain-Gate OFF Capacitance
Source-Gate OFF Capacitance
Drain-Gate Plus Source-Gate
ON Capacitance
Turn On Delay Time
Rise Time
Turn OFF Delay Time
Fall Time
108
109
110
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-3
-3
-3
nA
-3
-10
-2
-6
-0.5
-4
V
-25
-25
-25
80
40
10
mA
3
3
3
nA
8
12
18
Ω
15
15
15
15
85
4
1
6
30
4
1
6
30
15
85
4
1
6
30
15
85
pF
TEST CONDITIONS
V
DS
= 0V, V
GS
= -15V
V
DS
= 5V, I
D
= 1µA
V
DS
= 0V, I
G
= -1µA
V
DS
= 15V, V
GS
= 0V
V
DS
= 5V, V
GS
= -10V
V
DS
≤0.1V,
V
GS
= 0V
V
DS
= 0,
V
GS
= -10V
(Note 3)
f = 1MHz
V
DS
= V
GS
= 0
(Note 3)
Switching Time Test
Conditions (Note 3)
J107
J109
J110
V
DD
1.5V
1.5V
1.5V
V
GS(off)
-12V
-7V
-5V
R
L
150Ω 150Ω 150Ω
ns
NOTES: 1.
Approximately doubles for every 10
o
C increase in T
A
.
2.
Pulse test duration = 300µs; duty cycle
≤3%.
3.
For design reference only, not 100% tested.
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