CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
ACCURACY
Resolution
Integral Linearity Error
CA3338
CA3338A
Differential Linearity Error
CA3338
CA3338A
Gain Error
CA3338
CA3338A
Offset Error
DIGITAL INPUT TIMING
Update Rate
Update Rate
Set Up Time t
SU1
Set Up Time t
SU2
Hold Time t
H
Latch Pulse Width t
W
Latch Pulse Width t
W
OUTPUT PARAMETERS
Output Delay t
D1
Output Delay t
D2
Rise Time t
r
Settling Time t
S
Output Impedance
Glitch Area
Glitch Area
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE Clocked at 20MHz, R
L
≥
1 MΩ,
Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
See Figure 4
-
-
See Figure 4
-
-
Input Code = FF
HEX
, See Figure 3
-
-
Input Code = 00
HEX
; See Figure 3
To Maintain
1
/
2
LSB Settling
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
For Low Glitch
For Data Store
For Data Store
For Data Store
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
R
L
Adjusted for 1V
P-P
Output
From LE Edge
From Data Changing
10% to 90% of Output
10% to Settling to
1
/
2
LSB
V
REF
+ = 6V, V
DD
= 6V
V
REF
- = V
EE
= -2.5V,V
REF
+ = +2.5V
-
-
-
-
120
-
-
-
-
-
±1
±0.75
±0.75
±0.5
±0.75
±0.5
±0.25
Bits
-
-
LSB
LSB
-
-
LSB
LSB
-
-
-
LSB
LSB
LSB
DC
DC
-
-
-
-
-
50
20
-2
8
5
5
25
-
-
-
-
-
-
-
MHz
MHz
ns
ns
ns
ns
ns
25
22
4
20
160
150
250
-
-
-
-
200
-
-
ns
ns
ns
ns
Ω
pV/s
pV/s
3
CA3338, CA3338A
Electrical Specifications
PARAMETER
REFERENCE VOLTAGE
V
REF
+ Range
V
REF
- Range
V
REF
+ Input Current
SUPPLY VOLTAGE
Static I
DD
or I
EE
Dynamic I
DD
or I
EE
Dynamic I
DD
or I
EE
V
DD
Rejection
V
EE
Rejection
DIGITAL INPUTS
High Level Input Voltage
Low Level Input Voltage
Leakage Current
Capacitance
TEMPERATURE COEFFICIENTS
Output Impedance
NOTE:
2. Parameter not tested. but guaranteed by design or characterization.
-
200
-
ppm/×
o
C
LE = Low, D0 - D7 = High
LE = Low, D0 - D7 = Low
V
OUT
= 10MHz, 0V to 5V Square Wave
V
OUT
= 10MHz,
±2.5V
Square Wave
50kHz Sine Wave Applied
50kHz Sine Wave Applied
D0 - D7, LE, COMP
Note 2
Note 2
2
-
-
-
-
-
±1
5
-
0.8
±5
-
V
V
µA
pF
-
-
-
-
-
-
100
-
20
25
3
1
220
100
-
-
-
-
µA
µA
mA
mA
mV/V
mV/V
(+) Full Scale, Note 2
(-) Full Scale, Note 2
V
REF
+ = 6V, V
DD
= 6V
V
REF
- + 3
V
EE
-
-
-
40
V
DD
V
REF
+ - 3
50
V
V
mA
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE Clocked at 20MHz, R
L
≥
1 MΩ,
Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4
CA3338, CA3338A
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
D7
D6
D5
D4
D3
D2
D1
V
SS
D
0
V
EE
Digital Ground
Least Significant Bit. Input Data Bit
Analog Ground
Reference Voltage Negative Input
Analog Output
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
OUTPUT
VOLTAGE
DESCRIPTION
Most Significant Bit
Input
Data
Bits
(High = True)
INPUT
DATA
LATCH
ENABLE
t
D1
t
D2
90%
10%
1
/ LSB
2
t
S
t
r
1
/ LSB
2
V
REF
-
V
OUT
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
D2
gives the delay from the input changing to the output
changing (10%), while t
SU2
and t
H
give the set up and hold
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given t
SU1
set up time to the LE falling edge,
and the t
H
hold time from the LE rising edge. The delay to
the output changing, t
D1
, is now referred to the LE falling
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
W
pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
V
REF
+
Reference Voltage Positive Input
COMP
LE
V
DD
Data Complement Control input. Active High
Latch Enable Input. Active Low
Digital Power Supply, +5V
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2
0
) through D7 (weighted 2
7
),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
DD
and V
SS
, are shifted to operate between V
DD
and V
EE
. V
EE
optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
DD
and V
EE
supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
INPUT DATA
t
SU1
t
W
LATCH
ENABLE
LATCHED
DATA
FEEDTHROUGH
t
H
LATCHED
t
SU2
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
REF
- this is the (-) full-
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V
REF
+, the (+) full-scale reference.
In unipolar operation, V
REF
- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
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