DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD168111A
MICROSTEP DRIVER FOR DRIVING CAMERA LENS
DESCRIPTION
The
µ
PD168111A is a monolithic 2-channel H bridge driver that consists of a CMOS controller and a MOS output
stage. It can reduce the current consumption and the voltage loss at the output stage compared with a conventional
driver using bipolar transistors, thanks to employment of a MOS process.
can be substantially reduced during operation.
This product is ideal for driving the motor of a digital still camera as it can switch over between two-phase
excitation driving and microstep driving, using a stepper motor.
This product employs a P-channel
MOSFET on the high side of the output stage, eliminating a charge pump. As a result, the circuit current consumption
FEATURES
O Two H bridge circuits employing power MOSFET
O Current feedback 64-step microstep driving and two-phase excitation driving selectable
O Motor control by serial data (6 words of 16-bit configuration)
Data is input with the LSB first.
Pulse cycle, number of pulses, and output current value can be set.
O Input logic frequency: 6 MHz MAX.
O 3 V power supply
Minimum operating power supply voltage V
DD
= 2.7 V
O Undervoltage lockout circuit
Shuts down internal circuitry at V
DD
= 1.7 V TYP.
O Constrained output leak current
Built-in the shut off circuit of V
M
pin output leak current at V
DD
= 0 V.
O 24-pin TSSOP
ORDERING INFORMATION
Part Number
Package
24-pin plastic TSSOP (5.72 mm (225))
µ
PD168111AMA-6A5-A
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16536EJ1V0DS00 (1st edition)
Date Published May 2003 NS CP(K)
Printed in Japan
2003
µ
PD168111A
PIN FUNCTIONS
Package: 24-pin TSSOP
SCLK
SDATA
MOB
LGND
C
OSC
PGND2
OUT2B
V
M2
OUT2A
FB2
EXT0
EXT1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LATCH
OSC
IN
FIL2
V
DD
FIL1
FB1
OUT1B
V
M1
OUT1A
PGND1
EN
RESETB
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
SCLK
SDATA
MOB
LGND
C
OSC
PGND2
OUT2B
V
M2
OUT2A
FB2
EXT0
EXT1
RESETB
EN
PGND1
OUT1A
V
M1
OUT1B
FB1
FIL1
V
DD
FIL2
OSC
IN
LATCH
Serial clock input pin
Serial data input pin
Pin Function
Phase detection output pin
Control block GND pin
Pin connecting capacitor for output oscillator
Output block GND pin
Channel 2 output B
Motor power pin
Channel 2 output A
Channel 2 current detection resistor connecting pin
Logic block monitor output pin 1
Logic block monitor output pin 2
Reset input pin
Output enable pin
Output block GND pin
Channel 1 output A
Motor power pin
Channel 1 output B
Channel 1 current detection resistor connecting pin
Channel 1 filter capacitor connecting pin
Control block power pin
Channel 2 filter capacitor connecting pin
Original oscillation clock input pin
Serial data latch input pin
2
Data Sheet D16536EJ1V0DS
µ
PD168111A
BLOCK DIAGRAM
OSC
IN
23
RESETB
V
DD
V
M1
V
M2
13
21
SERIAL-PARALLEL DECODER
17
8
1/N
PULSE
GENERATOR
EXTOUT
SELECTOR
11
12
3
FILTER
–+
FILTER
EXT0
EXT1
MOB
SCLK
1
SDATA
2
LATCH
24
EVR1
C
OSC
LGND
5
4
OSC
+
EVR2
CURRENT SET
Internal Block
V
M
H BRIDGE
ch1
20
FIL1
14
EN
22
FIL2
9
7
6
PGND2
Current
Sense2
10
FB2
FB1
Current
19 Sense1
V
M
H BRIDGE
ch1
15
PGND1
16
18
OUT1A OUT1B
OUT2A OUT2B
Data Sheet D16536EJ1V0DS
3
µ
PD168111A
EXAMPLE OF STANDARD CONNECTION
CPU
OSC
IN
SCLK
SDATA LATCH
RESETB
V
DD
V
M1
3.3 V
V
M2
5V
C
OSC
330pF
LGND
Current
Sense1
V
M
H BRIDGE
ch1
FILTER
FILTER
V
M
H BRIDGE
ch2
OSC
1/N
PULSE
GENERATOR
EVR1 EVR2
CURRENT SET
EXTOUT
SELECTOR
EXT0
EXT1
MOB
100 kΩ
V
DD
SERIAL-PARALLEL DECODER
Internal Block
FB1
2 kΩ
Note 1
1000 pF
Note 2
Current
Sense2
FB2
2 kΩ
Note 1
1000 pF
Note 2
PGND
OUT1A OUT1B
FIL1
EN
FIL2
OUT2A OUT2B
PGND
1000 pF
1000 pF
from CPU
Note 3
Note 3
M
This circuit diagram is shown as an example and is not intended for mass production.
Connect a bypass capacitor between the power supply and GND pins for stabilization.
Notes 1.
Adjust the value of the external resistor according to the output current. The relationship between the
output current and external resistance is as follows.
Output current IOUT
≅
EVRMAX
÷
FB x 1000
2.
It is recommended to connect a capacitor to the FB pin for stabilization to suppress the electronic noise
superimposed on the pin.
3.
The capacitor connected to the FIL pin is used to suppress the voltage noise for stabilization. Adjust the
capacitance of the capacitor to effectively suppress the noise.
4
Data Sheet D16536EJ1V0DS
µ
PD168111A
COMMAND INPUT TIMING CHART
This IC controls the motor by transmitting serial control commands.
Here is an example of the commands.
Internal reset cleared
RESET
LATCH
SCLK
SDATA
External
reference
CLK
Start
point wait
Start point
excitation wait
Pulse output
EXT0
;;;; ; ;; ;
;;;;;;;;;;;;
;;;; ; ;; ;
Dummy data
D0
D1
D2
D3
16 bit
Initialization
setting
(wait value setting)
Pulse
setting,
etc.
Pulse
setting,
etc.
Pulse
setting,
etc.
All ‘0’
Output depending on
initialization setting
Output depending on
initialization setting
Synchronized with pulse timing
according to setting of D1
Synchronized with pulse timing
according to setting of D2
Driving period H set by D2
Driving period H set by D1
Pulse output
EXT1
This IC can change all commands by issuing the LATCH signal once. Therefore, “initialization setting” does not
have to be explicitly performed as shown in the above example.
Immediately after the reset has been cleared, dummy data must be transmitted according to the timing of the
transmit data. For details, refer to SERIAL INTERFACE SPECIFICATIONS.
Data Sheet D16536EJ1V0DS
5
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