NEC's LOW POWER
UPB1008K
GPS RF RECEIVER
FEATURES
• LOW POWER CONSUMPTION:
52 mW
• DUAL-CONVERSION IQ DOWN CONVERTER
1
:
Reference frequency: REF
in
= 27 MHz
• PSEUDO-BASEBAND WITH 2-BIT DIGITIZED OUTPUT
• ON-CHIP LNA, ON-CHIP FREQUENCY SYNTHESIZER,
IF AGC AMPLIFIER:
with 45 dB typical range of adjustable gain
• SMALL 36 PIN QFN PACKAGE:
Flat lead style for better RF performance
Note:
1. Based on eRide's proprietary GPS DSP architecture
BLOCK DIAGRAM
PIN 1 –
AGC
OSC
PD
1/2
UPB1008K
LNA
Dividers
IQ DEMO
ADC
ADC
1stMIX
APPLICATIONS
• E911 ENABLED MOBILE PHONE
• IN-VEHICLE NAVIGATION SYSTEMS
• LOW POWER HANDHELD GPS RECEIVER
• PC/PDA+GPS INTEGRATION
• ASSET TRACKING
DESCRIPTION
NEC's UPB1008K is a Silicon RFIC especially designed for
handheld low power/low cost GPS receivers. The IC com-
bines an LNA, followed by a double-conversion RF/IF
downconverter block and a PLL frequency synthesizer on one
chip. The second IF Freqency is a pseudo- baseband signal
into a on-chip 2-bit A/D converters.The device can operate on
a supply voltage as low as 2.7 V, and is a housed in a small 36
pin QFN (Quad, Flat, No-lead) package, resulting in a very low
power consumption and reduced board space.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
RF APPLICATION DIAGRAM
Nyquist Filters
1st Mixer
LNA
RF SAW
TANK
/2
/4
2-bit
ADC
IF filter
AGC
ISign
BASEBAND I C
2-bit
ADC
IMag
QSign
QMag
Loop
Filter
/6
/7
/2
PLL Frequency
Counters
I/Q
Balance
Regulator Circuitry
/8
/2
REFin
27 MHz
Reference
Clock
California Eastern Laboratories
UPB1008K
ADVANCED GPS COMPLETE SOLUTION
e
911
AUTOMOTIVE
e
YELLOW PAGES
PERSONAL GPS
ASSET
TRACKING
NETWORK
TRACKING
eRide NAVIGATION
SOFTWARE & DRIVERS
TEMP
TIME
FREQ
UART
GAIN
CONTROL
ADC
OPUS
STATE
MACHINE
PLL
ADC
eRide
SMART SERVER
ACQUISITION
TRACKING
UPB1008K
Opus 1
eRide WORLDWIDE
REFERENCE STATION
NETWORK
ADVANCED GPS COMPLETE SOLUTION
"NEC Corporation and eRide, Inc. have teamed to provide an advanced positioning solution delivering high GPS performance,
accuracy, integration and architecture flexibility. The chip set combines CEL's
UPB1008K
receiver IC with eRide's
Opus One
SOC
(System-on-a-Chip) Baseband ASIC and is suitable for standard GPS products as well as Cellular Handset applications. Also provided
are scalable client navigation software and drivers, plus location-aiding data from eRide's Smart Server. Together, they offer a
complete hardware/infrastructure solution.
The chip set's design allows it to operate independently of wireless interface standards - and independently of the host product's CPU
and Operating System. This unique approach to system integration makes it easy to deploy the chip set into an wireless application,
in any wireless network. A "Universal Hardware" solution, the design promises lower manufacturing costs and, ultimately lower cost
to the consumer.
The chip set's advanced positioning architecture offers unmatched sensitivity providing fast, accurate positioning architecture offers
unmatched sensitivity providing fast and accurate position fixes, even when indoors or in deep in urban canyons."
HIGH PERFORMANCE GPS OMNI MODE
LI, C/A code receiver
Performance
Time to First Fix w/ aiding
Time to First Fix w/o aiding
Accuracy
Sensitivity
Indoor
5-7sec
10-20sec
10-25m cep
-155dBm
in 1sec dwells
Outdoor
1-3sec
3-5sec
2-5m cep
-142dBm
in two 10msec dwells
Superior performance in high reflection indoor environments and in urban canyon types of outdoor environments
POWER DISSIPATION
First Fix
Tracking
Stand By
400 mW
200-300 mW
30 mW
UPB1008K
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C, V
CC
= 3.0 V, unless otherwise specified)
SYMBOLS
I
CC
V
CC
I
CC_PD
I
CC
rf
I
CC
lo
ICC pll
ICC bb
ICC if
ICC lna
PARAMETERS AND CONDITIONS
Total Circuit Current, No Signals
Supply Voltage
Power down current, PIN 13 = V
IL
RF Block Circuit Current (pin 3), No signal
VCO Block Circuit Current (pin 7), No signal
PLL Block Circuit Current (pin 9), No signal
Baseband Block Circuit Current (pin 23), No signal,
open load
IF Block Circuit Current (pin 28) , No signal
Pre-Amplifier Open Connector Current (pin 36),
No signal
UNITS
mA
V
µA
µA
mA
mA
mA
mA
mA
MIN
14
2.7
–
0.4
4.1
2.7
2.5
2.7
1.0
TYP
18
3.0
1
0.5
5.6
3.6
3.4
3.7
1.4
MAX
23.5
3.3
10
0.7
7.2
4.7
4.3
4.7
1.8
LNA/RF DOWNCONVERTER
(f
RFin
= 1575.42 MHz, f
1stLOin
= 1400 MHz, P
LO
= -10 dBm, f
1stIF
= 175 MHz, Pin 13: V
IL
= 3 V, Z
L
differential = 32Ω & Z
S
=
Γopt)
SYMBOLS
CG
LNA_MIX
NF
LNA_MIX
P
1dBLNA_MIX
Z
LNAin
Z
MIXout
A
LO-IF
A
LO-RF
PLL
SYMBOLS
I
CPOH
I
CPOL
f
PD
SYMBOLS
V
REFin
f
REF
VT
C/N
PARAMETERS AND CONDITIONS
PLL Charge Pump High Side Current @ V
CPout
= V
CC/
2
PLL Charge Pump Low Side Current @ V
CPout
= V
CC/
2
Phase Comparison Frequency
PARAMETERS AND CONDITIONS
Reference input minimum level
Input Frequency of Reference Input
VCO Control Voltage, PLL Locked
VCO C/N, 1kHz, Loop band width = 5 kHz
UNITS
µA
µA
MHz
UNITS
mVpp
MHz
V
dBc/Hz
MIN
–
–
–
MIN
50
–
0.8
57
TYP
200
-200
13.5
TYP
200
27
1.5
62
MAX
–
–
–
MAX
–
–
2.2
–
PARAMETERS AND CONDITIONS
Power conversion gain from 2nd LNA/mixer to 1st IF,
P
RFin
= -50 dBm
Noise Figure of 2nd LNA/mixer(SSB), Input matched
1 dB Compression refer to source, Input matched
RF Input Impedance of LNA
IF Output Impedance of Mixer
Local Signal Leak to IF, f
1stLOin
=1400 MHz,
P
LO
= 0 dBm
Local Signal Leak to RF, f
1stLOin
=1400 MHz,
P
LO
= 0 dBm
UNITS
dB
dB
dBm
Ohm
Ohm
dBm
dBm
MIN
18
–
–
–
–
–
TYP
23
5
-38
31
32
-35
-50
MAX
28
–
–
–
–
–
CRYSTAL OSCILLATOR/REVERENCE AMPLIFIER BLOCK
AGC AMPLIFIER, I-Q DEMODULATOR, and ADC BLOCK(f
1stIFin
= 175 MHz, Z
in
= 600Ω)
SYMBOLS
CG
AGC/MIX
PARAMETERS AND CONDITIONS
Maximum voltage conversion gain of AGC amplifier/
I-Q mixer, P
in
= -60 dBm, V
AGC
= 0.5 V, Unmatched
Minimum voltage conversion gain of AGC amplifier/
I-Q mixer, P
in
= -60 dBm, V
AGC
= 2.0 V, Unmatched
AGC control range, V
AGC
= 0.5 V to 2 V
1 dB compression input to AGC amplifier,
set voltage gain = 30 dB
AGC control voltage
UNITS
dB
dB
dB
dBm
V
MHz
V
dB
%
%
MIN
–
–
25
–
0.5
–
–
4.0
50
50
TYP
30
-15
45
-45
–
10
2.1
6.5
–
–
MAX
–
–
–
–
2.0
–
2.8
–
–
–
A
AGC/MIX
P
1dBAGC
V
AGC
BW
3dB Mixer Bandwidth
V
IQ-C
IQ BalanceControl Voltage, Gain(Ich) = Gain (Qch)
A
IQ-C
IQ Balance Control Gain Range, V
IQ-C
= 0 to 3 V
Duty
Ich Mag Bit Output Pulse Duty, P1stIFin = -84 dBm
Ich
V
AGC
= 0.5 V, V
IQ-C
= 0 V
Duty
Qch Mag Bit Output Pulse Duty, PIF2in = -88 dBm
Qch
V
AGC
= 0.5 V, V
IQ-C
= 0 V
BASEBAND AMPLIFIER BLOCK
(Z
S
= 2kΩ & Z
L
= 2 kΩ)
SYMBOLS
PARAMETERS AND CONDITIONS
V
BBOH
Baseband output logic high, C
L
= 10 pF
V
BBOL
Baseband output logic low, C
L
= 10 pF
UNITS
V
V
MIN
2.0
0
TYP
–
–
MAX
–
0.5
UPB1008K
ABSOLUTE MAXIMUM RATINGS
1,2
(T
A
= 25°C)
SYMBOLS
V
CC
P
D
T
OP
T
STG
I
CC_total
PARAMETERS
Supply Voltage
4
Total Power Dissipation
3
Operating Temperature
Storage Temperature
Total Circuit Current
4
UNITS
V
CC
mW
°C
°C
RATINGS
3.6
361
-40 to +85
-55 to +150
RECOMMENDED
OPERATING CONDITIONS
SYMBOLS
V
CC
T
OP
f
RFin
f
REFin
f
1st
LO
f
1stIFin
f
2ndLOin
V
IH
V
IL
PARAMETERS
Supply Voltage
Operating Temperature
RF Input Frequency
Reference Frequency
1st LO Oscillating
Frequency
1st IF Input Frequency
2nd LO Input Frequency
Power Down Control
Voltage "High"
Power Down Control
Voltage "Low"
UNITS MIN
V
2.7
°C
-40
MHz
MHz
MHz
MHz
MHz
V
V
2
0
TYP
3.0
+25
1575
27
1400
175
175
V
CC
0.5
MAX
3.3
+85
Notes:
1. Operation in excess of any one of these parameters may result
in permanent damage.
2. More than two items must not be reached simultaneously.
3. T
A
= +85°C, mounted on a 50 x 50 x 1.6 mm double-sided
copper clad epoxy glass PWB.
4. T
A
= 25°C
APPLICATION CIRCUIT
0.1uF
15pF
SAW
IN
OUT
INb
15pF
OUTb
1:16
VCC
1.2nH
200
0.1uF
GNDanalog
LNAbias
Mixout1
Mixout2
VCC
VAGC
IFin1
IFin2
Vref
VCCanalog
100nF
36
35
34
33
32
31
30
29
28
VCC
VCC
43K
.1pF
12pF
6.8nH
3.3nH
SAW
FILTER
RF_in
12pF
NE662MO4
100nF
GNDIo
4
24
300
MATCHING
NETWORK
VCC
GND1na
1
AGC
27
21FoutI
150pF
2
1stMIX
LNA
IQ_DEMO
LNAin
26
21Foutb
VCCrf
3
25
DCoffsetI
100nF
DCoffsetb
VCC
1stLO-OSC1
12pF
1stLO-OSC2
12pF
VCC
VCCIo
100nH
PDout
3.3nH
3.3nH
5
1/2
1/4
Vth
23
VCCbb
100nF
6
22
I_mag
OSC
7
1/2
2Bit ADC
21
I_sign
I_mag
Q_sign
I_sign
Q_sign
1/6.375
8
PD
2Bit ADC
1/2
20
9
19
Q_mag
Q_mag
D0
15K
15K
22pF
1.2K
Vccdig
CP
uPB1008K
Vagc
10
11
12
13
14
15
16
17
18
VCC
PD
0.01uF
DCoffsetQb
GNDdig
100nF
DCoffsetQ
21FoutQb
21FoutQ
GNDbb
Ic_cntl
ic_cntl
REFin
Refin
100nF
150pF
1OOnF
PD
UPB1008K
PIN FUNCTIONS
Pin No.
Symbol
Function and Application
Internal Equivalent Circuit
3
1
2
GNDlna
LNAin
Ground pin of LNA
2
36
Input pin of low noise amplifier. It is a
single-ended open collector design.
Capacitive coupling is required; external
matching will improve gain or NF.
Regulator
GND
Bias
r=6.5k
V
CC
1
3
VCCrf
Supply voltage pin of LNA, RF mixer and VCO
voltage regulator.
Ground pin of 1st LO Oscillator circuit and RF
Mixer.
Pin 5 & 6 are base pins of the differential
amplifier for 1st LO oscillator. These pins
require an LC (varacator) tank circuit to
oscillate at around 1400 MHz.
Supply voltage pin of oscillator circuit for
1st LO Oscillator and RF mixer
3
7
r = 410
4
GNDlo
c=1.8p
5
6
1stLO-OSC1
1stLO-OSC2
6
c=1.8p
r=300
r=300
5
V
CC
r=4.4k
r=4.4k
7
VCClo
Regulator
idc=941u
GND
Bias
4
8
PDout
This is a current mode charge pump output.
For connection to a passive RC loop filter for driving
external varactor diode of 1stLO-OSC.
Source Control
9
PFD
ESD
FROM PFD
9
VCCdig
Supply voltage pin of digital portion of the chip.
Source
8
Sink Control
PFD
Sink
ESD
11
10
REFin
Input pin of reference frequency buffer. This pin
should be equipped with external 27 MHz
oscillator (e.g. TCXO).
r=20k
ESD
9
r=20k
idc=9.7u
11
GNDdig
Ground pin of digital portion of the chip.
10
ESD
r=500
r=500
r=50k
r=30k
idc=22u
c=5.4p
11
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