Integrated
Circuit
Systems, Inc.
ICS9159-14
Frequency Generator and Integrated Buffer for PENTIUM™
General Description
The
ICS9159-14
generates all clocks required for high speed
RISC or CISC microprocessor systems such as 486, Pentium,
PowerPC,Ô etc. Four different reference frequency multiply-
ing factors are externally selectable with smooth frequency
transitions. These multiplying factors can be customized for
specific applications.
High drive BCLK outputs provide typically greater than 1V/
ns slew rate into 30pF loads. PCLK outputs provide typically
better than 1V/ns slew rate into 20pF loads while maintaining
±5% duty cycle.
•
•
•
•
Features
Generates up to four processor and six bus clocks, plus
disk, USB and reference clocks
Synchronous clocks skew matched to 250ps window on
PCLKs and 500ps window on BCLKs
3.0V - 5.5V supply range
28-pin SOIC package
Block Diagram
Pin Configuration
28-Pin SOIC
Functionality
FS1
0
0
1
1
FS0
0
1
0
1
*VCO
118/17 x
X1
65/7 x X1
92/11 x X1
69/9 x X1
X1, REF
(MHz)
14.318
14.318
14.318
14.318
CPU
(MHz)
50 (49.7)
66.6 (66.5)
60 (59.9)
55 (54.9)
*VCO range is limited from 60 - 200 MHz.
PCLK(0:3)
VCO/2
BCLK(0:5)
PCLK/2
USB
48 MHz
DISK
24 MHz
All frequencies in MHz, assuming 14.318 MHz input.
Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of Motorola Corporation.
9159-14 Rev B 3/16/00
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9159-14
Pin Descriptions
PIN NUMBER
1, 8, 26
2
3
4, 11, 23
6, 7, 9, 10
13, 12
14, 20
15, 16, 18 19,
21, 22
17
5
25
28, 27
PIN NAME
VDD
X1
X2
GND
PCLK(0:3)
FS(0:1)
VDD
BCLK(0:5)
GND
OEN
USB
REF(0:1)
TYPE
PWR
IN
OUT
PWR
OUT
IN
PWR
OUT
PWR
IN
OUT
OUT
DESCRIPTION
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, CPU and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table above.
Frequency multiplier select pins. See table above. These inputs have internal pull-up
devices.
Power for BCLK output buffers.
Bus clock outputs are fixed at one half the PCLK frequency.
Ground for BCLK output buffers.
OEN tristates all outputs when low. This input has an internal pull-up device. 24
DISK OUT The DISK controller clock is fixed at 24 MHz (with 14.318 MHz input).
The USB clock is fixed at 48 MHz (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input clock, nominally
14.31818 MHz.
2
ICS9159-14
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V
Logic Inputs ....................................................................... GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature ............................................................. 0°C to +70°C
Storage Temperature ........................................................................... –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
V
DD
= 3.0 – 3.7 V, T
A
= 0 – 70
°
C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current
1
Output High Current
1
Output Low Current
1
Output High Current
1
Output Low Voltage
1
Output High Voltage
1
Output Low Voltage
1
Output High Voltage
1
Supply Current
SYMBOL
VIL
VIH
IIL
IIH
IOL
IOH
IOL
IOH
VOL
VOH
VOL
VOH
IDD
VIN=0V
VIN=VDD
VOL=0.8V; for CPUs & BUSes
VOH=2.0V; for CPUs & BUSes
VOL=0.8V; for fixed CLKs
VOH=2.0V; for fixed CLKs
IOL=15mA; for CPUs & BUSes
IOH=-30mA; for CPUs & BUSes
IOL=12.5mA; for fixed CLKs
IOH=-20mA; for fixed CLKs
@66.5 MHz; all outputs unloaded
TEST CONDITIONS
MIN
-
0.7VDD
-28.0
-5.0
30.0
-
25.0
-
-
2.4
-
2.4
-
TYP
-
-
-10.5
-
47.0
-66.0
38.0
-47.0
0.3
2.8
0.3
2.8
55
MAX
0.2VDD
-
-
5.0
-
-42.0
-
-30.0
0.4
-
0.4
-
110
UNITS
V
V
mA
mA
mA
mA
mA
mA
V
V
V
V
mA
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9159-14
Electrical Characteristics at 3.3V
V
DD
= 3.1 – 3.7 V, T
A
= 0 – 70
°
C
AC Characteristics
PARAMETER
Rise Time
1
Fall Time
1
Rise Time
1
Fall Time
1
Duty Cycle
1
Jitter, One Sigma
1
Jitter, Absolute
1
Jitter, One Sigma
1
Jitter, Absolute
1
Input Frequency
1
Logic Input Capacitance
1
Crystal Oscillator Capacitance
1
Power-on Time
1
Frequency Settling Time
1
Clock Skew Window
1
Clock Skew Window
1
Clock Skew Window
1
SYMBOL
Tr1
Tf1
Tr2
Tf2
Dt
Tj1s1
Tjab1
Tj1s2
Tjab2
Fi
CIN
CINX
ton
ts
Tsk1
Tsk2
Tsk3
Logic input pins
X1, X2 pins
From VDD=1.6V to 1 st crossing of 66.5 MHz
VDD supply ramp < 40ms
From 1st crossing of acquisition to <
1% settling
CPU to CPU; Load=20pF; @1.4V
BUS to BUS; Load=20pF; @1.4V
CPU to BUS; Load=20pF; @1.4V
TEST CONDITIONS
20pF load, 0.8 to 2.0V CPU & BUS
20pF load, 2.0 to 0.8V CPU & BUS
20pF load, 20% to 80% CPU & BUS
20pF load, 80% to 20% CPU & BUS
20pF load @ VOUT=1.4V
CPU & BUS Clocks;
Load=20pF, FOUT>25 MHz
CPU & BUS Clocks;
Load=20pF, FOUT>25 MHz
Fixed CLK; Load=20pF
Fixed CLK; Load=20pF
MIN
-
-
-
-
45
-
-250
-
-5
12.0
-
-
-
-
-
-
1
TYP
0.9
0.8
1.5
1.4
50
50
-
1
2
14.318
5
18
2.5
2.0
150
300
2.6
MAX
1.5
1.4
2.5
2.4
55
150
250
3
5
16.0
-
-
4.5
4.0
250
500
5
UNITS
ns
ns
ns
ns
%
ps
ps
%
%
MHz
pF
pF
ms
ms
ps
ps
ns
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9159-14
Electrical Characteristics at 5.0V
V
DD
= 4.5 – 5.5 V, T
A
= 0 – 70
°
C
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current
1
Output High Current
1
Output Low Current
1
Output High Current
1
Output Low Voltage
1
Output High Voltage
1
Output Low Voltage
1
Output High Voltage
1
Supply Current
SYMBOL
VIL
VIH
IIL
IIH
IOL
IOH
IOL
IOH
VOL
VOH
VOL
VOH
IDD
VIN=0V
VIN=VDD
VOL=0.8V; for CPUs & BUSes
VOL=2.0V; for CPUs & BUSes
VOL=0.8V; for fixed CLKs
VOL=2.0V; for fixed CLKs
IOL=20mA; for CPUs & BUSes
IOH=-70mA; for CPUs & BUSes
IOL=15mA; for fixed CLKs
IOH=-50mA; for fixed CLKs
@66.5 MHz; all outputs unloaded
TEST CONDITIONS
MIN
-
2.4
-45
-5.0
36.0
-
30.0
-
-
2.4
-
2.4
-
TYP
-
-
-15
-
62.0
-152
50.0
-110.0
0.25
4.0
0.2
4.7
80.0
MAX
0.8
-
-
5.0
-
-90.0
-
-65.0
0.4
-
0.4
-
160.0
UNITS
V
V
µA
µA
mA
mA
mA
mA
V
V
V
V
mA
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
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