DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16707
263/256-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The
µ
PD16707 is a TFT-LCD gate driver equipped with 263/256-output lines. It can output a high-gate scanning voltage
in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also drive the
XGA / SXGA / SXGA+, and since the input signal is placed symmetrically, this product can wire easily between gate
drivers.
FEATURES
•
CMOS level input (2.3 to 3.6V)
•
263/256 outputs
•
High-output voltage (V
DD2
to V
EE
: 40 V MAX.)
•
Capable of All-ON outputting (/AOR, /AOL)
•
Input terminal symmetrical placement
•
Adapted to COG and TCP
Remark
/xxx indicates active low signal.
ORDERING INFORMATION
Part Number
Package
CHIP
TCP (TAB package)
µ
PD16707P
µ
PD16707N-xxx
Remark
Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representavies.
The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16411EJ1V0DS00 (1st edition)
Date Published January 2003 NS CP (K)
Printed in Japan
2003
µ
PD16707
2. PIN CONFIGURATION
2.1 CHIP PAKAGE :
µ
PD16707P Chip surface (Bump side)
Chip size : 1.06±0.02 x 16.01±0.02 [mm]
Chip thickness : 595±25 [
µ
m]
619pin
620pin
DUMMY
618pin
PASSR
CLKR
/AOR
R,/LR
V
DD1
605pin
603pin
DUMMY
604pin
STVR
V
SS
V
SS
Alignment Mark1
: 50 x 50
µ
m
coordinate : (267.5,
−7785)
(267.5, 7785)
Alignment Mark2
: 50 x 50
µ
m
1pin
602pin
DUMMY
OER
OER
DUMMY
V
EE
V
EE
V
EE
V
EE
DUMMY
V
DD2
V
DD2
V
DD2
V
DD2
DUMMY
DUMMY
V
DD1
V
DD1
DUMMY
V
EE
V
EE
V
EE
DUMMY
V
DD2
V
DD2
DUMMY
Y(+)
O
0
O
1
O
2
X(+)
O
262
O
263
O
264
DUMMY
V
DD2
V
DD2
DUMMY
V
EE
V
EE
V
EE
DUMMY
V
DD1
V
DD1
DUMMY
coordinate : (387.5,
−7785)
(387.5, 7785)
(0,0)
DUMMY
V
DD2
V
DD2
V
DD2
V
DD2
DUMMY
V
EE
V
EE
V
EE
V
EE
DUMMY
OEL
OEL
292pin
DUMMY
311pin
PASSL
/AOL
V
SS
CLKL
R,/LL
STVL
MODE
V
SS
294pin
DUMMY
293pin
295pin
308pin
DUMMY
310pin
Visual
direction
Bump
IC
309pin
Data Sheet S16411EJ1V0DS
3
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