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“Standard”:
2.
3.
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5.
6.
7.
8.
9.
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11.
12.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
DATA SHEET
µ
PD16855A/B/C/D
DUAL HIGH-SIDE SWITCH FOR USB APPLICATION
MOS INTEGRATED CIRCUIT
DESCRIPTION
This product is the power switch IC with over current limit, used for the power supply bus of the Universal-Serial-
Bus (USB).
2 circuit builds in the Pch power MOSFET in the switch part, and this product realizes low on resistance (100 mΩ
TYP.) respectively.
And the over current detection, the thermal-shutdown circuit, an under voltage locked-out (UVLO) circuit whose
functions are necessary in the Host/HUB-controller of the USB standard are built in.
And the over-current-detect result can be reported to the controller by flag-pin.
This product builds in each two circuits of the power switch, control-pins and flag-pins, and this IC can be able to
control the power supply bus in 2 USB port.
There are four kinds of this product by the input logic of the control signal and switch operation in over-current
detect.
FEATURES
• Pch power MOSFET, 2 circuit building in
• Over-current detection circuit is built in and its result is outputted from flag-pin (“L” active)
• Prevent from dropping power supply by over current limit circuit
• Thermal shutdown circuit building in
• Under Voltage Locked Out (UVLO) circuit building in
• Switch on/off control is possible by the control-pin.
• 8 pin DIP/SOP package
ORDERING INFORMATION
PART NO.
PACKAGE
8-pin plastic DIP (300mil)
8-pin plastic SOP (225mil)
8-pin plastic SOP (225mil)
8-pin plastic SOP (225mil)
8-pin plastic SOP (225mil)
µ
PD16855BC
µ
PD16855AG
µ
PD16855BG
µ
PD16855CG
µ
PD16855DG
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13020EJ1V0DS00 (1st edition)
Date Published February 1999 N CP(K)
Printed in Japan
©
1998
FPGA/CPLD
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