PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ
PD16332
40-BIT EL-PANEL DRIVER
The
µ
PD16332 is an EL panel row driver using a high breakdown voltage CMOS process. It consists of 40-bit
bidirectional shift registers, and a high breakdown voltage CMOS driver block. The logic block operates on a 5-V
power supply, designed to be connected directly to a microcontroller (CMOS level input). The driver block has a
250 V, 100 mA high breakdown voltage output, and both the logic block and driver block consist of CMOS,
allowing operation with low power consumption.
FEATURES
• High breakdown voltage CMOS structure
• High breakdown voltage, high current output (250 V, 100 mA MAX.)
• 40-bit directional shift registers on chip
• Data control by transfer clock (external)
• 80-pin plastic QFP (3-Direction Lead)
• Wide operating temperature range (T
A
= –40 to +85°C)
• /PC pin allows polarity of all driver outputs to be inverted.
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP
µ
PD16332GF-3L9
Remark
/xxx indicates active low signal.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. S13014EJ3V1PM00 (3rd edition)
Date Published November 1998 NS CP(K)
Printed in Japan
©
1997
µ
PD16332
BLOCK DIAGRAM
/PC
/OE
V
DD2
BLK
S
1
A
CLK
R,/L
RIGHT I/O
CLK
R,/L
40-bit shift
registers
V
DD2
B
LEFT I/O
S
40
O
40
V
SS2
O
1
V
SS2
2
Preliminary Product Information
µ
PD16332
PIN CONFIGURATION (Top View)
µ
PD16332GF-3L9
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
O
9
O
10
O
11
O
12
O
13
O
14
O
15
O
16
O
17
O
18
O
19
O
20
Note1
V
DD2
N.C.
Note1
V
SS2
Note1
V
SS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
O
40
O
39
O
38
O
37
O
36
O
35
O
34
O
33
O
32
O
31
O
30
O
29
O
28
O
27
O
26
O
25
O
24
O
23
O
22
O
21
Note1
V
DD2
N.C.
Note1
V
SS2
V
SS1
Note1
Notes 1.
Be sure to use all pins V
DD1
, V
DD2
, V
SS1
and V
SS2
. Use V
SS1
and V
SS2
at the same potential.
2.
Pin 33 is connected to the lead frame internally, and therefore be sure to leave it open.
Caution
Be sure to enter the power to V
DD1
, logic signal, and V
DD2
, in that order, and turn off the
power in the reverse order.
R,/L
V
DD1
CLK
N.C.
BLK
N.C.
A
N.C.
Note2
I.C.
B
/OE
N.C.
/PC
N.C.
V
DD1
N.C.
Preliminary Product Information
3
µ
PD16332
PIN CONFINGRATION
Pin Symbol
BLK
/OE
/PC
A
B
CLK
R,/L
Pin Name
Blanking input
Output enable input
Polarity change input
RIGHT data input
LEFT data input
Clock input
Shift control input
Pin Number
29
35
37
31
34
27
25
Description
Please refer to the TRUTH TABLE 2.
Please refer to the TRUTH TABLE 2.
/PC = L : Polarity of all outputs inverted
When R,/L = H,
When R,/L = L,
A: Input
B: Output
A: Output B: Input
Shift is executed on a rising edge.
H: Right shift mode
A
→
O
1
··· O
40
→
B
L: Left shift mode
B
→
O
40
··· O
1
→
A
250 V, 100 mA
MAX.
5 V ± 10 %
30 to 240 V
Connected to system GND
Connected to system GND
Connected to the lead frame internally
Be sure to leave it open.
O
1
to O
40
V
DD1
V
DD2
V
SS1
V
SS2
I.C.
High breakdown voltage output
Logic block power supply
Driver block power supply
Logic ground
Driver ground
Internal-connection
1 to 20, 45 to 64
26, 39
21, 44
24, 41
23, 42
33
N.C.
Free pins
22, 28, 30, 32, 36,
38, 40, 43
Non-connection
TRUTH TABLE 1 (SHIFT REGISTER BLOCK)
Input
R,/L
H
H
L
L
CLK
↑
H or L
↑
H or L
S
1
Output
S
40
Input
A
S
1
Input
Output
B
S
40
Output
Execution of right shift
Retained
Execution of left shift
Retained
Shift register
TRUTH TABLE 2 (DRIVER BLOCK)
DATA
×
×
×
L
H
H
BLK
H
H
×
L
L
L
/OE
L
L
H
L
L
L
/PC
H
L
×
×
H
L
On
H
L
Z
Z
H
L
Reference
All driver outputs are H.
All driver outputs are L.
All driver outputs are Z.
Remark
H : High Level , L : Low Level ,
×:
H or L , Z : High Inpedance ,
DATA : Contence of the Shift Register
4
Preliminary Product Information
µ
PD16332
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (T
A
= +25 °C, V
SS1
= V
SS2
= 0 V)
Item
Logic supply voltage
Driver supply voltage
Logic input voltage
Logic output voltage
Driver output voltage
Driver output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
V
DD1
V
DD2
V
I1
V
O1
V
O2
I
O2
P
D
T
A
T
stg.
Rating
–0.5 to +6.0
–0.5 to +250
–0.5 to V
DD1
+ 0.5
–0.5 to V
DD1
+ 0.5
–0.5 to V
DD2
+ 0.5
±100
1000
Note
–40 to +85
–65 to +150
Unit
V
V
V
V
V
mA
mW
°C
°C
Note
When T
A
≥
+25 °C, load should be alleviated at a rate of –8.0 mW/°C.
If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded.
Absolute maximum ratings,
therefore, specify the values exceeding which the product may be physically damaged. Be sure
to use the product within the range of the absolute maximum ratings.
Caution
RECOMMENDED OPERATING RANGE (T
A
= –40 to +85 °C, V
SS1
= V
SS2
= 0 V)
Item
Logic supply voltage
Driver supply voltage
Input voltage high
Input voltage low
Driver output current
Symbol
V
DD1
V
DD2
V
IH
V
IL
I
OH
I
OL
MIN.
4.5
30
0.7·V
DD1
0
TYP.
5.0
MAX.
5.5
240
V
DD1
0.2·V
DD1
–70
+70
Unit
V
V
V
V
mA
mA
ELECTRICAL CHARACTERISTICS
(T
A
= + 25 °C, V
DD1
= 4.5 to 5.5 V, V
DD2
= 240 V, V
SS1
= V
SS2
= 0 V)
Item
High level output voltage
Low level output voltage
High level output voltage
Symbol
V
OH1
V
OL1
V
OH21
V
OH22
Low level output voltage
V
OL21
V
OL22
3-state output current
Input leakage current
High level input voltage
Low level input voltage
Static consumption current
I
TL
I
IL
V
IH
V
IL
I
DD11
I
DD12
I
DD21
I
DD22
Logic, T
A
= +25 °C
Logic, T
A
= –40 to +85 °C
Driver, T
A
= +25 °C
Driver, T
A
= –40 to +85 °C
Condition
Logic, I
OH
= –1.0 mA
Logic, I
OL
= 1.0 mA
O
1
to O
40
, I
OH
= –10 mA
O
1
to O
40
, I
OH
= –70 mA
O
1
to O
40
, I
OL
= 10 mA
O
1
to O
40
, I
OL
= 70 mA
V
O2
= V
DD2
or V
SS2
V
I
= V
DD1
or V
SS1
0.7·V
DD1
0.2·V
DD1
100
1000
100
1000
MIN.
0.9·V
DD1
0
220
190
20
35
±10.0
±1.0
TYP.
MAX.
V
DD1
0.1·V
DD1
Unit
V
V
V
V
V
V
µ
A
µ
A
V
V
µ
A
µ
A
µ
A
µ
A
Preliminary Product Information
5
嵌入式系统
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