DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD160032A
480-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256 GRAY SCALES, mini-LVDS INTERFACE SUPPORTED)
DESCRIPTION
The
μ
PD160032A is a source driver for TFT-LCD’s that supports the display of 256 gray scales and employs mini-LVDS
interface. Which can realize a full-color display of 16,777,216 colors by output of 256 values
γ
-corrected by an internal
D/A converter and 10-by-2 external power modules. Because the output dynamic range is as large as V
SS2
+ 0.2 V to
V
DD2
−
0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal
with dot-line inversion, n-line inversion, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd
output pins and even output pins respectively output gray scale voltages of differing polarity. Because of the
<R>
incorporation of mini-LVDS interface, the data transfer speed has improved and the amount of wiring on the PWB (Print
Wired Board) has been significantly reduced.
FEATURES
•
Differential interface: CLK (1 pair), gray scale data (6 pair)
•
CMOS interface: STHR(L), R,/L, STB, SB, POL, V
sel1
, V
sel2
, SRC, ORC, RxBIAS, H_2DOT, MODE1, MODE2
•
480 outputs
•
Capable of outputting 256 values by means of 10-by-2 external power modules (20 units) and a D/A converter
•
Logic power supply voltage (V
DD1
): 2.7 to 3.6 V
•
Driver power supply voltage (V
DD2
): 10.0 to 16.5 V
•
High-speed data transfer: f
CLK
= 172 MHz MAX. (Internal data transfer speed when operating at V
DD1
= 2.7 V)
•
Output dynamic range: V
SS2
+ 0.2 V to V
DD2
−
0.2 V
•
Apply for dot-line inversion, n-line inversion
•
Output voltage polarity inversion function (POL)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
COF (COF package)
μ
PD160032AN-xxx
μ
PD160032ANL-xxx
Remark
The TCP’s/COF’s external shape are customized. To order the required shape, please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16815EJ1V0DS00 (1st edition)
The mark <R> shows major revised points.
Date Published February 2006 NS CP(K)
Printed in Japan
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2003
μ
PD160032A
1. BLOCK DIAGRAM
CLKA
CLKB
D0A
D0B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
SB
STHR
STHL
STB
D0 to D5
CLK
Serial parallel converter
RxBIAS
V
DD1A
V
SS1A
V
DD1D
V
SS1D
R,/L
Logic
controller
STHR
STHL
Bidirectional shift register
Latch
V0-V19
V
DD2
D/A converter
V
SS2
POL
SRC
ORC
MODE1, MODE2
Vsel1, Vsel2
H_2DOT
Voltage follower output
------ ----- -----------------
- -
-
-
S1 S2 S3
S480
Remark
/xxx indicates active low signals.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
S2
S479
S480
POL
10
Multi-
plexer
8-bit D/A converter
V0
:
V9
V10
:
V19
10
2
Data Sheet S16815EJ1V0DS
μ
PD160032A
<R>
3. PIN CONFIGURATION (
μ
PD160032AN-xxx: TCP (TAB package), Copper Foil Surface, Face-up)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
VSS2
VDD2
V19
V18
V17
V16
V15
V14
V13
V12
V11
V10
(VDD1D)
SB
(VSS1D)
MODE1
(VDD1D)
R,/L
(VSS1D)
(VDD1D)
VSEL1
(VSS1D)
VSEL2
(VDD1D)
MODE2
(VSS1D)
RXBIAS
(VDD1D)
VSS1D
VSS1A
D5B
D5A
(VSS1A)
D4B
D4A
(VSS1A)
D3B
D3A
(VSS1A)
CLKB
CLKA
(VSS1A)
D2B
D2A
(VSS1A)
D1B
D1A
(VSS1A)
D0B
D0A
(VSS1A)
VDD1A
VDD1D
SRC
(VSS1D)
STB
POL
STHL
STHR
(VDD1D)
ORC
(VSS1D)
(VDD1D)
TEST
(VSS1D)
(VDD1D)
H_2DOT
(VSS1D)
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
VDD2
VSS2
H_2DOT
S480
S479
S478
Chip Bump side
S3
S2
S1
Remark
This figure does not specify the TCP package.
(V
DD1D
) and (V
SS1D
) are available for supply to logic input pin. Please don’t use these pins for power supply pin
with dynamic current. In addition, (V
DD1D
) and (V
SS1D
) can be left open. It recommends connecting (V
SS1A
) to the
low-pressure analog GND on PWB.
Data Sheet S16815EJ1V0DS
3
μ
PD160032A
<R>
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S1 to S480
D0A, D0B
D1A, D1B
D2A, D2B
D3A, D3B
D4A, D4B
D5A, D5B
CLKA,
CLKB
R,/L
Shift direction
control
Shift clock
Input
(mini-LVDS)
Input
(CMOS)
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift): STHR input, S1→S480, STHL output
R,/L = L (left shift): STHL input, S480→S1, STHR output
STHR
STHL
Right shift start
pulse
Left shift start pulse
I/O
(CMOS)
This is the start pulse I/O pin when connected in cascade. Loading of display data
starts when a high level is read.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
For details of the timing, refer to
6. FUNCTION DESCRIPTION.
STB
POL
SB
RxBIAS
Latch
Polarity
Bus-line set-back
mini-LVDS receiver
bias voltage control
SRC
Slew-rate control
Input
(CMOS)
Input
(CMOS)
Input
(CMOS)
Input
(CMOS)
Input
(CMOS)
ORC
MODE1,
MODE2
Output resistance
control
Output reset control
Input
(CMOS)
Input
(CMOS)
Change the input mode, latched the registered data and transfer to DAC at the
rising edge. And supplied voltage to LCD pixel is output at falling edge.
Control the polarity of the driver output.
Refer to
Table 4−3.
Change the input data order of mini-LVDS.
Refer to
Table 4−1.
This pin controls the bias current of mini-LVDS receiver circuit.
RxBIAS = H: Normal power
RxBIAS = L: Low power
SRC = H: High-slew-rate mode
Internal analog current becomes higher during STB = H period.
SRC = L: Normal-slew-rate mode
ORC = H: Low output resistance mode
ORC = L: High output resistance mode
This pin controls the output reset function, in other words charge sharing.
MODE1
L
L
H
H
MODE2
L
H
L
H
Setting prohibited
Output reset only after POL changed in STB input
Output reset, every STB input
Output Reset
Output reset invalid
Shift clock input.
Pin Name
Driver
Gray scale data
I/O
Output
Input
(mini-LVDS)
Input pin with gray-scale data.
As for relation with SB signal, refer to
Table 4−1.
Description
The D/A converted 256-gray-scale analog voltage is output.
A setup of MODE1 = L and MODE2 = H is setting prohibited (
μ
PD160032A
becomes a test mode and does not perform normal specification operation).
Fore more details, refer to
8. OUTPUT RESET FUNCTION (MODE).
4
Data Sheet S16815EJ1V0DS
μ
PD160032A
(2/2)
Pin Symbol
H_2DOT
Pin Name
Horizontal 2 dots/1
dot inversion select
V
sel1
V
DD2
select
I/O
Input
(CMOS)
Input
(CMOS)
V
sel2
Output amp.
capability setting
V
0
-V
19
Input
(CMOS)
−
Description
H_2DOT = H: 2 dots inversion in horizontal
H_2DOT = L: 1 dot inversion in horizontal
Refer to
7. RELATIONSHIP BETWEEN POL AND H_2DOT.
Select the following setting according to the voltage inputted into V
DD2
.
V
sel1
= L: V
DD2
= 10.0 to 12.5 V
V
sel1
= H: V
DD2
= 12.5 to 16.5 V
This pin can change the drive capability of output amplifier.
V
sel2
= L: Low power mode (drive capability: Small)
V
sel2
= H: Normal power mode (driver capability: Large)
Input the
γ
-corrected power supplies from outside. Make sure to maintain the
following relationships. During the gray scale voltage output, be sure to keep the
gray scale level power supply at a constant level.
V
DD2
−
0.2 V
≥
V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
≥
0.5 V
DD2
0.5 V
DD2
≥
V
10
> V
11
>V
12
> V
13
> V
14
> V
15
> V
16
>V
17
> V
18
> V
19
≥
V
SS2
+ 0.2 V
V
DD1D
V
DD1A
V
DD2
V
SS1D
V
SS1A
V
SS2
Low-voltage logic
power supply
Low-voltage analog
power supply
Driver power supply
Low-voltage logic
ground
Low-voltage analog
ground
Driver ground
−
−
−
−
−
−
2.7 to 3.6 V
V
DD1D
and V
DD1A
should be same electric potential.
2.7 to 3.6 V
V
DD1D
and V
DD1A
should be same electric potential.
10.0 to 16.5 V
Ground for internal logic circuit.
Please wire V
SS1D
and V
SS1A
in external circuit boards
.
Ground for internal mini-LVDS receiver circuit.
Please wire V
SS1D
and V
SS1A
in external circuit boards
.
Ground for internal high voltage circuit.
γ
-corrected power
supplies
Cautions 1. The power start sequence must be [V
DD1
→logic
input
→V
DD2
& V
0
-V
19
] in that order. Reverse this
sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert bypass, etc capacitor between V
DD1
-V
SS1
and
V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion of a bypass
capacitor is also advised between the
γ
-corrected power supply pins (V
0
, V
1
, V
2
,....., V
19
) and V
SS2
.
Data Sheet S16815EJ1V0DS
5
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