CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
W, U versions respectively
-20
V
CC
= 3.3V @ +25°C
85
10/10/25
Voltage at pin from GND to V
CC
0.1
1
MIN
(Note 12)
TYP
(Note 2)
10, 50
+20
MAX
(Note 12)
UNIT
kΩ
%
Ω
pF
µA
PARAMETER
R
H
to R
L
Resistance
R
H
to R
L
Resistance Tolerance
R
W
C
H
/C
L
/C
W
I
LkgDCP
Wiper Resistance
Potentiometer Capacitance
Leakage on DCP Pins
RESISTOR MODE
R
INL
(Note 7)
Integral Non-linearity
DCP register set between 20 hex and 7F hex.
Monotonic over all tap positions (Note 3)
DCP register set between 20 hex
and 7F hex. Monotonic over all tap
positions (Note 3)
W option
U option
-2
-1
-1
0
0
±0.25
±0.1
±0.1
1
0.5
±45
2
1
1
3
2
MI
(Note 4)
MI
(Note 4)
MI
(Note 4)
MI
(Note 4)
MI
(Note 4)
ppm/°C
R
DNL
(Note 6) Differential Non-linearity
R
OFFSET
(Note 5)
Offset
W option
U option
TC
R
(Notes 8, 9)
Resistance Temperature
Coefficient
DCP register set between 20 hex and 7F hex
(Note 3)
Operating Specifications
SYMBOL
I
CC1
I
SB
I
ComLkg
t
DCP
(Note 9)
V
CC
Ramp
PARAMETER
V
CC
Supply Current
(Volatile Write/Read)
V
CC
Current (Standby)
Common-Mode Leakage
DCP Wiper Response Time
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
V
CC
= +5.5V, I
2
C Interface in Standby State
Voltage at SDA pin at GND or V
CC
SCL falling edge of last bit of DCP Data Byte to
wiper change
0.2
500
MIN
(Note 12)
TYP
(Note 2)
MAX
(Note 12) UNIT
200
µA
500
3
nA
µA
ns
V
CC
Ramp Rate
V/ms
3
FN8244.4
August 26, 2008
ISL90726
Operating Specifications
SYMBOL
t
D
(Continued)
TEST CONDITIONS
V
CC
above V
POR
, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby
state
MIN
(Note 12)
TYP
(Note 2)
MAX
(Note 12) UNIT
3
ms
PARAMETER
Power-up Delay
SERIAL INTERFACE SPECIFICATIONS
V
IL
(Note 10)
V
IH
(Note 10)
Hysteresis
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer
HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW
Voltage, Sinking 4mA
SDA, and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time
at SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
-0.3
0.3*V
CC
V
CC
+ 0.3
V
0.7*V
CC
0.05*V
CC
0
V
V
V
OL
Cpin (Note 9)
f
SCL
t
IN
t
AA
t
BUF
0.4
V
10
400
50
pF
kHz
ns
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of V
CC
, until
Data Valid
SDA exits the 30% to 70% of V
CC
window.
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
From 30% to 70% of V
CC
From 70% to 30% of V
CC
1300
900
ns
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
1300
600
600
ns
ns
ns
START Condition Hold Time
600
ns
Input Data Setup Time
100
ns
t
HD:DAT
t
SU:STO
t
HD:STO
t
DH
Input Data Hold Time
0
ns
STOP Condition Setup Time
600
ns
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
600
ns
0
ns
t
R
(Note 11)
t
F
(Note 11)
SDA and SCL Rise Time
20 +
0.1*Cb
20 +
0.1*Cb
250
ns
SDA and SCL Fall Time
250
ns
4
FN8244.4
August 26, 2008
ISL90726
Operating Specifications
SYMBOL
Cb (Note 11)
(Continued)
TEST CONDITIONS
Total on-chip and off-chip
MIN
(Note 12)
10
TYP
(Note 2)
MAX
(Note 12) UNIT
400
pF
PARAMETER
Capacitive Loading of SDA or
SCL
SDA and SCL Bus Pull-up
Resistor Off-chip
Rpu (Note 11)
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2kΩ ~ 2.5kΩ.
For Cb = 40pF, max is about 15kΩ ~ 20kΩ.
1
kΩ
NOTES:
2. Typical values are for T
A
= +25°C and 3.3V supply voltage.
3. LSB: [V(R
W
)
127
– V(R
W
)
0
]
/
127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
4. MI =
|
R
127
– R
0
|
/
127. R
127
and R
0
are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
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