Ordering number : ENA1189
LC871HC8A,LC871H96A
CMOS IC
128K/96K-byte ROM and 16384-byte RAM integrated
8-bit 1-chip Microcontroller
with USB-host controller
Overview
http://onsemi.com
The LC871HC8A/96A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 83.3ns, integrates on a single chip a number of hardware features such as 128K/96K-byte ROM, 16384-byte RAM,
a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit
timers or PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, 3 channels of
synchronous SIO interface with automatic data transfer capabilities, an asynchronous/synchronous SIO interface, a
UART interface (full duplex), a full-speed USB interface (host control function), an 8-bit 12-channel AD converter, 2
channels of 12-bit PWM, a system clock frequency divider, an infrared remote control receiver circuit, and a 40-
source 10-vector interrupt feature.
Features
ROM
•
131072
×
8 bits (LC871HC8A)
•
98304
×
8 bits (LC871H96A)
RAM
•
16384
×
9 bits
Bus
Cycle Time
•
83.3ns (When CF=12MHz)
Note: The bus cycle time here refers to the ROM read speed.
Minimum
Instruction Cycle Time (tCYC)
•
250ns (When CF=12MHz)
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.01
52108HKIM 20080402-S00005 No.A1189-1/27
LC871HC8A/96A
Ports
•
I/O ports
Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07)
•
USB ports
2 (UHD+, UHD-)
•
Dedicated oscillator ports
2 (CF1, CF2)
•
Input-only port (also used for oscillation)
1 (XT1)
•
Reset pins
1 (RES)
•
Power supply pins
6 (VSS1 to 3, VDD1 to 3)
Timers
•
Timer 0: 16-bit timer/counter with 2 capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
×
2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(lower-order 8 bits may be used as a PWM output)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
SIO
•
SIO0: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units)
(Suspension and resumption of data transmission possible in 1 byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
•
SIO4: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units)
(Suspension and resumption of data transmission possible in 1 byte units or in word units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
Continued on next page.
No.A1189-2/27
LC871HC8A/96A
Continued from preceding page.
•
SIO9: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units)
(Suspension and resumption of data transmission possible in 1 byte units or word units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
Full
Duplex UART
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
AD
Converter: 8 bits
×
12 channels
PWM:
Multifrequency 12-bit PWM
×
2 channels
Infrared
Remote Control Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the base clock)
2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding.
3) X'tal HOLD mode reset function
USB
Interface (host control function)
1) Compliant with full-speed (12M bps) specifications
2) Supports 4 transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer).
Audio
Interface
1) Sampling frequency (fs):
32kHz, 44.1kHz, 48kHz
2) Master clock frequency (internal PLL): 12.288MHz, 16.9344MHz, 18.432MHz
3) Bit clock selectable:
48fs/64fs
4) Data bit length:
16/18/20/24 bits
5) LSB first/MSB firsts selectable
6) Left-justification/right-justification selectable
Watchdog
Timer
•
Watchdog timer using external RC circuitry
•
Interrupt and reset signals selectable
Clock
Output Function
1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected
as the system clock.
2) Can output the source oscillation clock for the subclock.
No.A1189-3/27
LC871HC8A/96A
Interrupts
•
40 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4/UHC bus active/remote control signal receive
INT3/INT5/base timer
T0H/INT6/UHC device connected/UHC disconnected/UHC resume
T1L/T1H/INT7/SIO9/AIF start
SIO0/UART1 receive
SIO1/SIO4/UART1 transmit/end of AIF
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL
Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: 8192 levels maximum (The stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
Oscillation
and PLL Circuits
•
RC oscillation circuit (internal):
•
CF oscillation circuit:
•
Crystal oscillation circuit:
•
PLL circuit (internal):
For system clock
For system clock
For system clock, time-of-day clock
For USB interface (see Fig.5)), audio interface (see Fig. 6)
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the lower level.
(2) Reset generated by watchdog timer
(3) Interrupt generation
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
2) There are five ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Reset generated by watchdog timer
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(4) Having an interrupt source established at port 0
(5) Having an bus active interrupt source established in the USB host controll circuit
Continued on next page.
No.A1189-4/27
LC871HC8A/96A
Continued from preceding page.
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are seven ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Reset generated by watchdog timer
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
(6) Having an bus active interrupt source established in the USB host controll circuit
(7) Having an interrupt source established in the infrared remote controller receiver circuit
Package
Form
•
SQFP48(7×7): Lead-free type
Development
Tools
•
On-chip debugger: TCB87- type-B + LC87F1HC8A
Package Dimensions
unit : mm (typ)
3163B
9.0
7.0
36
37
25
24
48
1
0.5
(0.75)
12
0.18
13
7.0
9.0
1.7max
0.1
(1.5)
SANYO : SQFP48(7X7)
0.5
0.15
No.A1189-5/27
嵌入式系统
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