CAT93C46B
1-Kb Microwire Serial
EEPROM
Description
The CAT93C46B is a 1−Kb Serial EEPROM memory device which
is configured as either 64 registers of 16 bits (ORG pin at V
CC
) or 128
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C46B features a
self−timed internal write with auto−clear. On−chip Power−On Reset
circuit protects the internal logic against powering up in the wrong
state.
Features
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High Speed Operation: 4 MHz
1.8 V (1.65 V*) to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Self−Timed Write Cycle with Auto−Clear
Sequential Read
Software Write Protection
Power−up Inadvertant Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin PDIP, SOIC, TSSOP and 8−pad UDFN and TDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant
†
V
CC
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
V, W** SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8**
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATIONS
CS
SK
DI
DO
1
V
CC
NC
NC
V
CC
ORG CS
SK
GND
1
ORG
GND
DO
DI
PDIP (L), SOIC (V, X),
TSSOP (Y), UDFN (HU4),
TDFN (VP2)**
(Top View)
SOIC (W)**
(Top View)
** Not recommended for new designs.
PIN FUNCTION
ORG
CS
SK
DI
CAT93C46B
DO
Pin Name
CS
SK
DI
DO
GND
V
CC
GND
ORG
NC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
Figure 1. Functional Symbol
*CAT93C46Bxx−xxL (T
A
=
−205C
to +855C)
†For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Note: When the ORG pin is connected to V
CC
, the
x16 organization is selected. When it is connected
to ground, the x8 organization is selected. If the
ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
January, 2014
−
Rev. 3
1
Publication Order Number:
CAT93C46B/D
CAT93C46B
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Value
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
Parameter
Supply Current (Write)
Supply Current (Read)
Standby Current
(x8 Mode)
Standby Current
(x16 Mode)
Input Leakage Current
(V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +125°C, V
CC
= +1.65 V to +5.5 V, T
A
=
−20°C
to +85°C unless otherwise specified.)
Test Conditions
Write, V
CC
= 5.0 V
Read, DO open, f
SK
= 2 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
CS = GND, ORG = GND
V
IN
= GND or V
CC
CS = GND,
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.65 V
≤
V
CC
< 4.5 V
1.65 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 3 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
=
−400
mA
1.65 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
1.65 V
≤
V
CC
< 4.5 V, I
OH
=
−100
mA
V
CC
−
0.2
2.4
0.2
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−0.1
2
0
V
CC
x 0.7
Min
Max
1
500
2
5
1
3
1
2
1
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
V
V
V
V
V
V
V
V
mA
mA
mA
Units
mA
mA
mA
I
LI
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN CAPACITANCE
(T
A
= 25°C, f = 1 MHz, V
CC
= 5 V)
Symbol
C
OUT
(Note 4)
C
IN
(Note 4)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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2
CAT93C46B
Table 5. A.C. CHARACTERISTICS
(V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +125°C, V
CC
= +1.65 V to +5.5 V, T
A
=
−20°C
to +85°C unless otherwise specified.)
V
CC
< 3.3 V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 5)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program / Erase Cycle Time
WRITE, ERASE
WRAL, ERAL
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
DC
Parameter
Min
50
0
100
100
0.25
0.25
100
3
5
0.1
0.1
0.1
0.1
4000
Max
V
CC
> 3.3 V
T
A
=
−405C
to +855C
Min
50
0
50
50
0.1
0.1
100
3
5
ms
ms
ms
ms
kHz
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
5. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. POWER−UP TIMING
(Notes 6 and 7)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
0.1
0.1
Units
ms
ms
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
v
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
4.5 V
v
V
CC
v
5.5 V
4.5 V
v
V
CC
v
5.5 V
1.65 V
v
V
CC
v
4.5 V
1.65 V
v
V
CC
v
4.5 V
Current Source I
OLmax
/I
OHmax
; C
L
= 100 pF
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3
CAT93C46B
Device Operation
The CAT93C46B is a 1024−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C46B can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 9−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10−bit instructions control the reading, writing and erase
operations of the device. The CAT93C46B operates on a
single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
during a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organization).
Table 8. INSTRUCTION SET
Address
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL*
WRAL*
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
x8
A6−A0
A6−A0
A6−A0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
x16
A5−A0
A5−A0
A5−A0
11XXXX
00XXXX
10XXXX
01XXXX
D7−D0
D15−D0
D7−D0
D15−D0
x8
Data
x16
Comments
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
Read
Upon receiving a READ command (Figure 3) and an
address (clocked into the DI pin), the DO pin of the
CAT93C46B will come out of the high impedance state and,
after sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable after
the specified time delay (t
PD0
or t
PD1
).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is proceeded by a dummy zero bit.
All sunsequent data words will follow without a dummy
zero bit.
Erase/Write Enable and Disable
The CAT93C46B powers up in the write disable state.
Any writing after power−up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device is
removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46B write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status. The
EWEN and EWDS instructions timing is shown in Figure 4.
* Not available at V
CC
< 1.8 V
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4
CAT93C46B
t
SKHI
SK
t
DIS
DI
t
CSS
CS
t
DIS
DO
t
PD0
, t
PD1
DATA VALID
t
CSMIN
VALID
VALID
t
DIH
t
SKLOW
t
CSH
Figure 2. Synchronous Data Timing
SK
CS
A
N
DI
1
1
0
t
PD0
DO
HIGH−Z
A
N−1
A
0
Don’t Care
Dummy 0
D
15 . . .
D
0
or
D
7 . . .
D
0
Address +
1
D
15 . . .
D
0
or
D
7 . . .
D
0
Address +
2
D
15 . . .
D
0
or
D
7 . . .
D
0
Address + n
D
15 . . .
or
D
7 . . .
Figure 3. Read Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
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