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IS62VV25616LL-70T

产品描述Standard SRAM, 256KX16, 70ns, CMOS, PDSO44, TSOP2-44
产品类别存储    存储   
文件大小88KB,共10页
制造商Integrated Silicon Solution ( ISSI )
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IS62VV25616LL-70T概述

Standard SRAM, 256KX16, 70ns, CMOS, PDSO44, TSOP2-44

IS62VV25616LL-70T规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
零件包装代码TSOP2
包装说明TSOP2-44
针数44
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间70 ns
I/O 类型COMMON
JESD-30 代码R-PDSO-G44
JESD-609代码e0
长度18.41 mm
内存密度4194304 bit
内存集成电路类型STANDARD SRAM
内存宽度16
功能数量1
端子数量44
字数262144 words
字数代码256000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织256KX16
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TSOP2
封装等效代码TSOP44,.46,32
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源1.8 V
认证状态Not Qualified
座面最大高度1.2 mm
最大待机电流0.000005 A
最小待机电流1 V
最大压摆率0.02 mA
最大供电电压 (Vsup)2.25 V
最小供电电压 (Vsup)1.7 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.8 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度10.16 mm
Base Number Matches1

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IS62VV25616L/LL
256K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 70, 85, 100 ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 1.65V-1.95V V
CC
power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (7.2mm x 8.7mm)
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION
NOVEMBER 2000
The
ISSI
IS62VV25616L and IS62VV25616LL are
high-speed, 4,194,304 bit static RAMs organized as
262,144 words by 16 bits. They are fabricated using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
For the IS62VV25616L/LL, when
CE
is HIGH (deselected)
or
CE
is low and both
LB
and
UB
are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62VV25616L and IS62VV25616LL are packaged in
the JEDEC standard 44-pin TSOP (Type II) and 48-pin
mini BGA (7.2mm x 8.7mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
11/30/00
Rev. 00C
1

 
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