The AS7C1026Q and AS7C31026Q are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20 ns with output enable access times (t
OE
) of 6, 7, 8 ns are ideal for high-
performance applications.
When CE is high the devices enter standby mode. The AS7C1026Q is guaranteed not to exceed 55 mW power consumption in CMOS standby
mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the rising
edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with
the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers
stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026Q) or 3.3V supply (AS7C31026Q). the
device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest
possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 7 mm × 11 mm.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
AS7C1026Q
AS7C31026Q
Both
Both
Both
Both
Both
Symbol
V
t1
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–0.50
–
–65
–55
–
Max
+7.0
+5.0
V
CC
+0.50
1.0
+150
+125
20
Unit
V
V
V
W
°
C
°
C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
L
L
L
L
L
WE
X
H
H
H
L
L
L
H
X
OE
X
L
L
L
X
X
X
H
X
LB
X
L
H
L
L
L
H
X
H
UB
X
H
L
L
L
H
L
X
H
I/O0–I/O7
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
High Z
High Z
I/O8–I/O15
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
D
IN
High Z
Mode
Standby (I
SB
), I
SBI
)
Read I/O0–I/O7 (I
CC
)
Read I/O8–I/O15 (I
CC)
Read I/O0–I/O15 (I
CC
)
Write I/O0–I/O15 (I
CC
)
Write I/O0–I/O7 (I
CC
)
Write I/O8–I/O15 (I
CC
)
Output disable (I
CC
)
Key:
H = High, L = Low, X = don’t care.
10/29/02, v. 0.9.0
Alliance Semiconductor
P. 2 of 10
AS7C1026Q
AS7C31026Q
®
Recommended operating conditions
Parameter
Supply voltage
Device
AS7C1026Q
AS7C31026Q
AS7C1026Q
Input voltage
AS7C31026Q
Both
Ambient operating temperature
commercial
industrial
Symbol
V
CC
V
CC
V
IH
V
IH
V
IL1
T
A
T
A
Min
4.5
3.0
2.2
2.0
–0.5
0
–40
Nominal
5.0
3.3
–
–
–
–
–
Max
5.5
3.6
V
CC
+ 0.5
V
CC
+ 0.5
0.8
70
85
Unit
V
V
V
V
V
o
o
C
C
1 V
IL
min. = –3.0V for pulse width less than t
RC
/2.
DC operating characteristics (over the operating range)
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