operating on a single 5 V power source and having a
131072 words
×
16 bits configuration. Equipped with
large capacity capabilities, high speed transfer rates and
low power dissipation, this series is suited for a wide
variety of applications ranging from computer main
memory and expansion memory to commercial
equipment.
Address input utilizes a multiplexed address bus which
permits it to be enclosed in a compact plastic package of
SOJ 40-pin, SOP 40-pin, and TSOP 44-pin . Refresh rates
are within 8 ms with 512 row address (A0 to A7, A8R)
selection and support Row Address Strobe (RAS)-only
refresh, Column Address Strobe (CAS)-before-RAS
refresh and hidden refresh settings. There are functions
such as fast page mode, read-modify-write and byte write.
The pin assignment follows the JEDEC 1 M DRAM
(65536 words
×
16 bits, 1CAS/2WE) standard.
• Package:
SOJ 40-pin (400 mil) plastic package : LC322271J
SOP 40-pin (450 mil) plastic package: LC322271M
TSOP 44-pin (400 mil) plastic package : LC322271T
Package Dimensions
unit: mm
3200-SOJ40
[LC322271J]
Features
•
•
•
•
•
•
•
•
•
131072 words
×
16 bits configuration.
Single 5 V ± 10% power supply.
All input and output (I/O) TTL compatible.
Supports fast page mode, read-modify-write and byte
write.
Supports output buffer control using early write and
Output Enable (OE) control.
8 ms refresh using 512 refresh cycles.
Supports RAS-only refresh, CAS-before-RAS refresh
and hidden refresh.
Follows the JEDEC 1 M DRAM (65536 words
×
16
bits, 1CAS/2WE) standard.
RAS access time/column address time/CAS access
time/cycle time/power dissipation
LC322271J, M, T
-70
RAS access time
Column address access time
CAS access time
Cycle time
Power dissipation (max.)
During operation
During standby
70 ns
35 ns
20 ns
130 ns
688 mW
-80
80 ns
45 ns
30 ns
150 ns
633 mW
SANYO: SOJ40
Parameter
5.5 mW (CMOS level)/11 mW (TTL level)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
32896HA (OT)/33195TH (OT) No. 5085-1/29
LC322271J, M, T-70/80
Package Dimensions
unit: mm
3195-SOP40
[LC322271M]
unit: mm
3207-TSOP44
[LC322271T]
SANYO: SOP40
SANYO: TSOP44 (TYPE II)
Pin Assignments
No. 5085-2/29
LC322271J, M, T-70/80
Block Diagram
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Output short-circuit current
Operating temperature range
Storage temperature range
LC322271J, M
LC322271T
I
OUT
Topr
Tstg
Symbol
V
CC
max
V
IN
V
OUT
Pd max
Ratings
–1.0 to +7.0
–1.0 to +7.0
–1.0 to +7.0
800
700
50
0 to +70
–55 to +150
mA
°C
°C
1
1
1
Unit
V
V
V
mW
Note
1
1
1
1
Note: 1. Stresses greater than the above listed maximum values may result in damage to the device.
No. 5085-3/29
LC322271J, M, T-70/80
DC Recommended Operating Ranges
at Ta = 0 to +70°C
Parameter
Power supply voltage
Input high level voltage
Input low level voltage
(A0 to A7, A8R, RAS, CAS, UW, LW, OE)
Input low level voltage (I/O1 to I/O16)
Note: 2. All voltages are referenced to V
SS
.
*:
–2.0 V when pulse width is less than 20 ns.
Symbol
V
CC
V
IH
V
IL
V
IL
min
4.5
2.4
–1.0
*
–0.5
*
typ
5.0
max
5.5
6.5
+0.8
+0.8
Unit
V
V
V
V
Note
2
2
2
2
DC Electrical Characteristics
at Ta = 0 to +70°C, V
CC
= 5 V ± 10%
LC322271J, M, T
Parameter
Symbol
Conditions
min
Operating current
(Average current during operation)
Standby current
RAS-only refresh current
Fast page mode current
Standby current
CAS-before-RAS refresh current
Input leakage current
Output leakage current
Output high level voltage
Output low level voltage
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
IL
I
OL
V
OH
V
OL
RAS, CAS, address cycling: t
RC
= t
RC
min
RAS = CAS = V
IH
RAS cycling, CAS = V
IH
: t
RC
= t
RC
min
RAS = V
IL
, CAS, address cycling: t
PC
= t
PC
min
RAS = CAS = V
CC
– 0.2 V
RAS, CAS cycling: t
RC
= t
RC
min
0 V
≤
V
IN
≤
6.5 V, pins other than test pin = 0 V
D
OUT
disable, 0 V
≤
V
OUT
≤
5.5 V
I
OUT
= –2.5 mA
I
OUT
= 2.1 mA
–10
–10
2.4
0.4
-70
max
125
2
125
115
1
125
+10
+10
–10
–10
2.4
0.4
min
-80
max
115
2
115
90
1
115
+10
+10
mA
mA
mA
mA
mA
mA
µA
µA
V
V
3
3, 5
3, 4, 5
3, 4, 5
Unit
Note
Note: 3. All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here, current value
becomes smaller.
4. I
CC1
and I
CC4
are dependent on output loads. Maximum values for I
CC1
and I
CC4
represent values with output open.
5. Address change is less than or equal to one time during RAS = V
IL
. Concerning I
CC4
, it is less than or equal to one time during 1 cycle (t
PC
).
AC Electrical Characteristics
at Ta = 0 to +70°C, V
CC
= 5 V ± 10% (Notes 6, 7 and 8)
Parameter
Random read, write cycle time
Read-write/read-modify-write cycle time
Fast page mode cycle time
Fast page mode read-write/read-modify-write cycle time
RAS access time
CAS access time
Column address access time
CAS precharge access time
Output low-impedance time from CAS low
Output buffer turn-off delay time
Rise, fall time
RAS precharge time
RAS pulse width
RAS pulse width for fast page mode cycle only
Symbol
t
RC
t
RWC
t
PC
t
PRWC
t
RAC
t
CAC
t
AA
t
CPA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RASP
0
0
3
50
70
70
10000
100000
20
50
-70
min
130
190
45
95
70
20
35
40
0
0
3
60
80
80
10000
100000
20
50
max
min
150
200
55
100
80
30
45
50
-80
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9, 14, 15
9, 14
9, 15
9
9
10
Note
Continued on next page.
No. 5085-4/29
LC322271J, M, T-70/80
Continued from preceding page.
-70
Symbol
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
CP
t
ASR
t
RAH
t
ASC
t
CAH
t
AR
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
REF
t
WCS
t
CWD
t
RWD
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPT
t
ROH
t
OEA
t
OED
t
OEZ
t
OEH
t
DZC
t
DZO
t
MCS
t
MRH
t
MCH
15
0
20
0
0
0
0
0
0
50
100
65
70
10
15
10
40
15
20
15
0
20
0
0
0
0
0
15
min
20
70
20
25
17
10
10
0
12
0
15
50
40
0
0
0
15
50
15
25
20
0
15
50
8
0
50
100
65
70
10
15
10
40
15
25
10000
50
35
max
min
30
80
30
25
17
10
10
0
12
0
20
60
45
0
0
0
15
60
15
25
20
0
20
60
8
10000
50
35
-80
max
Parameter
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
CAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Column address hold time referenced to RAS
Column address to RAS lead time
Read command setup time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command hold time referenced to RAS
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data input setup time
Data input hold time
Data input hold time referenced to RAS
Refresh time
Write command setup time
CAS to UW, LW delay time
RAS to UW, LW delay time
Column address to UW, LW delay time
CAS precharge UW, LW delay time for fast page mode
cycle only
CAS setup time for CAS-before-RAS
CAS hold time for CAS-before-RAS
RAS precharge CAS active time
CAS precharge time for CAS-before-RAS counter test
我编译时CPU_NAME报错，汇编代码如下：
;; Copyright (c) Microsoft Corporation. All rights reserved.;;; Use of this source code is subject to the terms of the Microsoft end-user; lic ......
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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