CMOS IC
LC876880B/72B/64B
8-Bit Single Chip Microcontroller
Under-Development
LC876880B
8-bit Single Chip Microcontroller incorporating 80KB ROM and 2048 byte RAM on chip
LC876872B
8-bit Single Chip Microcontroller incorporating 72KB ROM and 2048 byte RAM on chip
LC876864B
8-bit Single Chip Microcontroller incorporating 64KB ROM and 2048 byte RAM on chip
Overview
The LC876880B/72B/64B are 8-bit single chip microcomputers with the following on-chip functional blocks:
- CPU: operable at a minimum bus cycle time of 100ns
- On-chip ROM Maximum Capacity:
LC876880B
80K bytes
LC876872B
72K bytes
LC876864B
64K bytes
- On-chip RAM: 2048 bytes
- VFD automatic display controller / driver
- 16-bit timer / counter (can be divided into two 8 bit timers)
- 16-bit timer / counter (can be divided into two 8 bit timers / two 8 bit PWM)
- Four 8-bit timers with prescaler
- Timer for use as date / time clock
- High-speed clock counter
- System clock divider function
- Two synchronous serial I/O port (with automatic block transmit / receive function)
- Asynchronous / synchronous serial I/O port
- 14-channel × 8-bit AD converter
- Weak signal detector
- 22-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Ver:1.04
S0204
September，02, 2004 SYSTEM-BIS Div.
T.Kawata 1/27
LC876880B/72B/64B
Features
(1) Read-Only Memory (ROM):
LC876880B
LC876872B
LC876864B
81920
×
8bits
73728
×
8bits
65536
×
8bits
(2) Random Access Memory (RAM): 2048 × 9 bits (LC876880B/72B/64B)
(3) Minimum Bus Cycle Time: 100ns (10MHz) VDD=3.0½5.5[V]
250ns (4MHz)
VDD=2.5½3.0[V]
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time(tCYC): 300ns (10MHz)
750ns (4MHz)
VDD=3.0½5.5[V]
VDD=2.5½3.0[V]
(5) Ports
- Input/output ports
Data direction programmable for each bit individually :
Oscillator
- 14V withstand input/output ports
Data direction programmable in nibble units :
(When N-channel open drain output is selected, data can
Data direction programmable for each bit individually :
- Input port (Oscillator) :
- VFD output ports
Large current outputs for digits :
Large current outputs for digits / segments :
digit / segment outputs :
segment outputs :
Other functions
Input/output ports :
Input ports :
- Oscillator pins :
- Reset pin :
- Power supply :
- VFD power supply :
24 (P1n, P70 to P73, P8n, SI2Pn)
1 (XT2)
8 (P0n)
be input in bit units.)
4 (P32 to P35)
1 (XT1)
9 (S0 / T0 to S8 / T8)
7 (S9 / T9 to S15 / T15)
8 (S16 to S23)
28 (S24 to S51)
12 (PFn, PG0 to PG3)
24 (PCn, PDn, PEn)
2 (CF1, CF2)
1 (RES#)
6 (VSS1 to VSS2, VDD1 to VDD4)
1 (VP)
(6) VFD automatic display controller
- Programmable segment/digit output pattern
Output can be switched between digit/segment waveform output (pins 9 to 24 can be used for
output of digit waveforms).
parallel-drive available for large current VFD.
- 16-step dimmer function available
(7) Weak signal detection (MIC signals etc)
- Counts pulses with width greater than a preset value
- 2 bit counter
2/27
LC876880B/72B/64B
(8) Timers
- Timer 0: 16-bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit
Counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
- Timer 1: PWM / 16-bit timer / counter with toggle output
Mode 0: 8-bit timer with 8-bit prescaler (and toggle output) + 8-bit timer / counter with 8-bit
prescaler (and toggle output)
Mode 1: 2 channel 8-bit PWM with 8-bit prescaler
Mode 2: 16-bit timer / counter with 8-bit prescaler (and toggle output) (Toggle output also
possible using the lower order 8 bits)
Mode 3: 16-bit timer with 8-bit prescaler (and toggle output) (The lower order 8 bits can be
used as PWM output)
-
-
-
-
Timer
Timer
Timer
Timer
4:
5:
6:
7:
8-bit
8-bit
8-bit
8-bit
timer
timer
timer
timer
with
with
with
with
6-bit
6-bit
6-bit
6-bit
prescaler
prescaler
prescaler (and toggle output)
prescaler (and toggle output)
- Base Timer
1) The clock signal can be selected from any of the following.
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts can be selected to occur at one of five different times.
(9) High speed clock counter
1) Capable of counting maximum: 20MHz clock (Using main clock 10MHz)
2) Real time output
(10) Serial-interface
- SIO 0: 8-bit synchronous serial Interface
1) LSB first / MSB first function available
2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 Tcyc)
3) Consecutive automatic data communication (1½256 bits (communication available for each
bit) (stop and reopening available for each byte))
- SIO 1: 8-bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2½512 Tcyc)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8½2048 Tcyc)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2½512 Tcyc)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
- SIO 2: 8-bit synchronous serial Interface
1) LSB first
2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 Tcyc)
3) Consecutive automatic data communication (1½32 bytes (communication available for each
byte)
3/27
LC876880B/72B/64B
(11) AD converter: 8 bits × 14 channels
- Analog reference voltage can selected from VDD1 or VDD2
(12) Remote control receiver circuit (connected to P73/INT3/T0IN terminal)
- Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc)
(13) Watchdog timer
- The watching timer period is set using an external RC.
- Watchdog timer can produce interrupt, system reset.
(14) Interrupts: 22-source, 10-vectored interrupts
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,
an equal or lower priority interrupt request is refused.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes
precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector
Selectable Level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/Base timer/INT5
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1/SIO2
9
00043H
H or L
ADC/MIC/T6/T7
10
0004BH
H or L
VFD automatic display controller/Port0/T4/T5
Priority Level: X>H>L
For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels: 1024 levels max. (Stack is located in RAM.)
(16) Multiplication and division
- 16 bit × 8 bit
(executed in 5 cycles)
- 24 bit × 16 bit (12 cycles)
- 16 bit ÷ 8 bit
(8 cycles)
- 24 bit ÷ 16 bit (12 cycles)
(17) Oscillation circuits
- On-chip RC oscillation circuit for system clock use.
- On-chip CF oscillation circuit for system clock use. (R
f
built in)
- On-chip Crystal oscillation circuit low speed system clock use. (Rd, R
f
external)
(18) System clock divider function
- Able to reduce current consumption
Available minimum instruction cycle time: 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs,
38.4µs, 76.8µs. (Using 10MHz main clock)
4/27
LC876880B/72B/64B
(19) Clock output function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
(20) Standby function
- HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral
circuits still operate but VFD display and some serial transfer operations stop.
1) Oscillation circuits are not stopped automatically.
2) Release occurs on system reset or by interrupt.
- HOLD mode
HOLD mode is used to reduce power consumption. Both program execution and peripheral
circuits are stopped.
1) CF, RC and crystal oscillation circuits stop automatically.
2) Release occurs on any of the following conditions.
(1) Input to the reset pin goes “Low”
(2) A specified level is input to at least one of INT0, INT1, INT2, INT4, and INT5
(3) An interrupt condition arises at port 0
- X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base-timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator is maintained in its state at HOLD mode inception.
3) Release occurs on any of the following conditions.
(1) Input to the reset pin goes “Low”
(2) A specified level is input to at least one of INT0, INT1, INT2, INT4, and INT5
(3) An interrupt condition arises at port 0
(4) An interrupt condition arises at the base-timer
(21) Factory shipment
- Delivery form QIP100E (LEAD FREE PRODUCT)
(22) Development tools
- Evaluation chip
- Emulator
: LC87EV690
: EVA62S + ECB876600D + SUB876800 + POD100QFP
: ICE-B877300 + SUB876800 + POD100QFP
- Flash ROM adapter : W87FQ100
(23) Same package and pin assignment as flash ROM version.
1) LC876800 series options can be set using flash ROM data(But Pull-down resistor isn’t
On-chip S32½S47). Thus testing and evaluation of mass production boards is possible.
2) The flash version has the ability to emulate the RAM and ROM capacity of the mask ROM
version.
5/27
51单片机
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