CY8C9520A
CY8C9540A, CY8C9560A
20, 40, and 60 Bit I/O Expander with
EEPROM
Features
■
■
Overview
The CY8C95xxA is a multi-port I/O expander with on board user
available EEPROM and several PWM outputs. All devices in this
family operate identically but differ in I/O pins, number of PWMs,
and internal EEPROM size.
The CY8C95xxA operates as two I
2
C slave devices. The first
device is a multi port I/O expander (single I
2
C address to access
all ports through registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to
disable the EEPROM. The EEPROM uses 2-byte addressing to
support the 28 Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I
2
C address
or by specific register addressing.
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.
The individual data pins can be configured as open drain or
collector, strong drive (10 mA source, 25 mA sink), resistively
pulled up or down, or high impedance. The factory default config-
uration is pulled up internally.
The system master writes to the I/O configuration registers
through the I
2
C bus. Configuration and output register settings
are storable as user defaults in a dedicated section of the
EEPROM. If user defaults were stored in EEPROM, they are
restored to the ports at power up. While this device can share the
bus with SMBus devices, it can only communicate with I
2
C
masters. The I
2
C slave in this device requires that the I
2
C master
supports clock stretching.
There is one dedicated pin that is configured as an interrupt
output (INT) and can be connected to the interrupt logic of the
system master. This signal can inform the system master that
there is incoming data on its ports or that the PWM output state
was changed.
The EEPROM is byte readable and supports byte-by-byte
writing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The
configuration registers can also disable EEPROM operations.
The CY8C95xxA has one fixed address pin (A0) and up to six
additional pins (A1-A6), which allow up to 128 devices to share
a common two wire I
2
C data bus. The Extendable Soft
Addressing algorithm provides the option to choose the number
of pins needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)
independently configurable 8-bit PWMs. These PWMs are listed
as PWM0-PWM15. Each PWM can be clocked by one of six
available clock sources.
For details on how to configure I
2
C, see Application Note
"Communication - I
2
C Port Expander with Flash Storage -
AN2304" at
http://www.cypress.com.
I
2
C interface logic electrically compatible with SMBus
Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)
I/O data pins independently configurable as inputs, outputs,
Bi-directional input/outputs, or PWM outputs
4/8/16 PWM sources with 8-bit resolution
Extendable soft addressing algorithm allowing flexible I
2
C
address configuration
Internal 3-/11-/27-Kbyte EEPROM
User default storage, I/O port settings in internal EEPROM
Optional EEPROM write disable (WD) input
Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes
Internal power on reset (POR)
Internal configurable watchdog timer
■
■
■
■
■
■
■
■
Top Level Block Diagram
WD
EEPROM
User
Settings
Area
User
Available
Area
Clocks
32 kHz
24 MHz
1.5 MHz
GPort 1
GPort 0
8 Bit IO
93.75 kHz
Divider (1-255)
GPort 2
5 Bit IO
3 Bit IO
or A4-A6
4 Bit IO
or A1-A3, WD6
PWM 0
Control
Unit
GPort 3
8 Bit IO
PWM 15
GPort 7
8 Bit IO
SCL
SDA
V
dd
V
ss
Power-on-Reset
INT
A0
Cypress Semiconductor Corporation
Document Number: 38-12036 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•408-943-2600
Revised December 14, 2010
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CY8C9520A
CY8C9540A, CY8C9560A
Contents
Architecture .............................................................3
Applications ........................................................3
Device Access Addressing ....................................4
Serial EEPROM Device ......................................4
Multi Port I/O Device ...........................................4
Document Conventions ..........................................4
Acronyms ............................................................4
Units of Measure ................................................4
Numeric Naming .................................................4
Pinouts .....................................................................5
28-Pin Part Pinout ..............................................5
48-Pin Part Pinout ..............................................6
100-Pin Part Pinout ............................................7
Pin Descriptions ......................................................9
Extendable Soft Addressing ...............................9
Interrupt Pin (INT) ...............................................9
Write Disable Pin (WD) .......................................9
External Reset Pin (XRES) .................................9
Working with PWMs ...........................................9
Register Mapping Table ........................................11
Register Descriptions ...........................................11
Input Port Registers (00h - 07h) .......................11
Output Port Registers (08h - 0Fh) ....................11
Int. Status Port Registers (10h - 17h) ...............12
Port Select Register (18h) ................................12
Interrupt Mask Port Register (19h) ...................12
Select PWM Register (1Ah) ..............................12
Inversion Register (1Bh) ...................................12
Port Direction Register (1Ch) ...........................12
Drive Mode Registers (1Dh-23h) ......................12
PWM Select Register (28h) ..............................12
Config (29h) ......................................................13
Period Register (2Ah) .......................................13
Pulse Width Register (2Bh) ..............................13
Divider Register (2Ch) ......................................13
Enable Register (2Dh) ......................................13
Device ID/Status Register (2Eh) .......................13
Watchdog Register (2Fh) .................................14
Command Register (30h) .................................14
Commands Description ........................................14
Store Config to E2 POR Defaults Cmd (01h) ...14
Restore Factory Defaults Cmd (02h) ................14
Write E2 POR Defaults Cmd (03h) ...................14
Read E2 POR Defaults Cmd (04h) ...................15
Write Device Config Cmd (05h) ........................15
Read Device Config Cmd (06h) ........................15
Reconfigure Device Cmd (07h) ........................15
Electrical Specifications .......................................16
Absolute Maximum Ratings ..............................16
Operating Temperature ....................................16
DC Electrical Characteristics ............................17
AC Electrical Characteristics ............................19
Packaging Dimensions .........................................21
Thermal Impedances ........................................23
Solder Reflow Peak Temperature ....................23
Features and Ordering Information .....................24
Ordering Code Definitions ................................24
Acronyms ...............................................................25
Reference Documents ..........................................25
Document Conventions ........................................25
Units of Measure ..............................................25
Numeric Conventions .......................................25
Glossary .................................................................26
Document History Page ........................................31
Sales, Solutions, and Legal Information .............32
Worldwide Sales and Design Support ..............32
Products ...........................................................32
PSoC Solutions ................................................32
Document Number: 38-12036 Rev. *E
Page 2 of 32
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CY8C9520A
CY8C9540A, CY8C9560A
Architecture
The
Top Level Block Diagram on page 1
illustrates the device
block diagram. The main blocks include the control unit, PWMs,
EEPROM, and I/O ports. The control unit executes commands
received from the I
2
C bus and transfers data between other bus
devices and the master device.
The on chip EEPROM can be separated conventionally into two
regions. The first region is designed to store data and is available
for byte wide read/writes through the I
2
C bus. It is possible to
prevent write operations by setting the WD pin to high. All
EEPROM operations can be blocked by configuration register
settings. The second region allows the user to store the port and
PWM default settings using special commands. These defaults
are automatically reloaded and processed after device power on.
The number of I/O lines and PWM sources are listed in the
following table.
Table 1. GPIO Availability
Port
GPort 0
GPort 1
GPort 2
GPort 3
GPort 4
GPort 5
GPort 6
GPort 7
PWMs
CY8C9520A
8 bit
5-8 bit
[1]
0-4 bit
[1]
–
–
–
–
–
4
CY8C9540A
8 bit
5-8bit
[1]
0-4it
[1]
8 bit
8 bit
4 bit
–
–
8
CY8C9560A
8 bit
5-8 bit
[1]
0-4 bit
[1]
8 bit
8 bit
8 bit
8 bit
8 bit
16
Figure 1. Logical Structure of the I/O Port
GPortx
7 Drive Mode
Registers
Output
Register
DriveMode
Pull-Up
Data
DriveMode
High Z
PWMs
Select PWM
Interrupt
Status
Input Register
Interrupt
Mask
8 Bit IO
Pin Direction
Inversion
There are four pins on GPort 2 and three on GPort 1 that can be
used as general purpose I/O or EEPROM Write Disable (WD)
and I
2
C-address input (A1-A6), depending on configuration
settings.
Figure 1
shows the single port logical structure. The Port Drive
Mode register gives the option to select one of seven available
modes for each pin separately: pulled up/down, open drain
high/low, strong drive fast/slow, or high impedance. By default
these configuration registers store values setting I/O pins to be
pulled up. The Invert register enables inversion of the logic of the
Input registers separately for each pin. The Select PWM register
assigns pins as PWM outputs. All of these configuration registers
are read/writable using corresponding commands in the
multi-port device.
The Port Input and Output registers are separated. When the
Output register is written, the data is sent to the external pins.
When the Input register is read, the external pin logic levels are
captured and transferred. As a result, the read data can be
different from written Output register data. This enables imple-
mentation of a quasi-bidirectional input-output mode, when the
corresponding binary digit is configured as pulled up/down
output.
Each port has an Interrupt Mask register and an Interrupt Status
register. Each high bit in the Interrupt Status register signals that
there has been a change in the corresponding input line since
the last read of that Interrupt Status register. The Interrupt Status
register is cleared after each read. The Interrupt Mask register
enables/disables activation of the INT line when input levels are
changed. Each high in the Interrupt Mask register masks
(disables) an interrupt generated from the corresponding input
line.
Applications
Each GPIO pin can be used to monitor and control various board
level devices, including LEDs and system intrusion detection
devices.
The on board EEPROM can be used to store information such
as error codes or board manufacturing data for read-back by
application software for diagnostic purposes.
Note
1. This port contains configuration-dependant GPIO lines or A1-A6 and WD lines.
Document Number: 38-12036 Rev. *E
Page 3 of 32
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CY8C9520A
CY8C9540A, CY8C9560A
Device Access Addressing
Following a start condition, the I
2
C master device sends a byte
to address an I
2
C slave. This address accesses the device in the
CY8C95xx. By default there are two possible address formats in
binary representation: 010000A0X and 101000A0X. The first is
used to access the multi port device and the second to access
the EEPROM. If additional address lines (A1-A6) are used then
the Device Addressing.
Table 2
defines the device addresses.
This addressing method uses a technique called Extendable Soft
Addressing, described in the section
Extendable Soft
Addressing on page 9.
Table 2. Device Addressing
Multi-Port Device
01
0
0
0
0
0
A
6
1
1
1
1
A
5
A
5
0
0
0
0
0
0
0
0
0
A
2
0
A
1
A
1
A
1
A
1
A
1
A
1
A
0
A
0
A
0
A
0
A
0
A
0
A
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
0
0
0
0
0
A
5
space is reached, then further writes are responded to with a
NAK.
Refer to
Figure 6
on page 10, which illustrates memory reading
and writing procedures for the EEPROM device.
Multi Port I/O Device
This device allows the user to set configurations and I/O opera-
tions through internal registers.
Each data transfer is preceded by the command byte. This byte
is used as a pointer to a register that receives or transmits data.
Available registers are listed in
Table 7
on page 11.
Document Conventions
EEPROM Device
1
1
1
1
A
4
A
4
A
4
0
0
0
A
3
A
3
A
3
A
3
0
0
A
2
A
2
A
2
A
2
A
2
0
A
1
A
1
A
1
A
1
A
1
A
1
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
Acronyms
Table 3
lists the acronyms that are used in this document.
Table 3. Acronyms
Acronym
AC
DC
EEPROM
direct current
electrically erasable programmable read-only
memory (E
2
)
general purpose I/O
input/output
most-significant bit
power on reset
pulse width modulator
Description
alternating current
A
3
A
2
A
4
A
3
A
2
A
4
A
3
A
2
A
4
A
3
A
2
A
6
A
5
When all address lines A1-A6 are used, the device being
accessed is defined by the first byte following the address in the
write transaction. If the most significant bit (MSb) of this byte is
‘0’, this byte is treated as a command (register address) byte of
the multi-port device. If the MSb is ‘1’, this byte is the first of a
2-byte EEPROM address. In this case, the device masks the
MSb to determine the EEPROM address.
GPIO
I/O
MSb
POR
PWM
Serial EEPROM Device
EEPROM reading and writing operations require 2 bytes, AHI
and ALO, which indicate the memory address to use.
To read one or more bytes, the master device addresses the unit
with a write cycle (= 0) to send AHI followed by ALO, readdresses
the unit with a read cycle (= 1), and reads one or more data bytes.
Each data byte read increments the internal address counter by
one up to the end of the EEPROM address space. A read or write
beyond the end of the EEPROM address space must result in a
NAK response by the Port Expander.
To write data to the EEPROM, the master device performs one
write cycle, with the first two bytes being AHI followed by ALO.
This is followed by one or more data bytes. In the case of block
writing it is advisable to set the starting address on the beginning
of the 64-byte boundary, for example 01C0h or 0080h, but this is
not mandatory. When a 64-byte boundary is crossed in the
EEPROM, the I
2
C clock is stretched while the device performs
an EEPROM write sequence. If the end of available EEPROM
Units of Measure
A units of measure table is located in the Electrical Specifications
section.
Table 17
on page 16 lists all the abbreviations used in
Section 4.
Numeric Naming
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are
decimal.
Document Number: 38-12036 Rev. *E
Page 4 of 32
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CY8C9520A
CY8C9540A, CY8C9560A
Pinouts
The CY8C95xxA device is available in a variety of packages, which are listed and illustrated in the following tables.
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
GPort0_Bit0_PWM3
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
V
SS
I
2
C Serial Clock (SCL)
I
2
C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
V
SS
GPort2_Bit2_PWM0/WD
INT
GPort2_Bit1_PWM0/A2
GPort2_Bit0_PWM2/A3
XRES
GPort1_Bit7_PWM0/A4
GPort1_Bit6_PWM2/A5
GPort1_Bit5_PWM0/A6
GPort1_Bit4_PWM2
GPort1_Bit3_PWM0
GPort1_Bit2_PWM2
GPort1_Bit1_PWM0
GPort1_Bit0_PWM2
V
dd
Description
Port 0, Bit 0, PWM 3.
Port 0, Bit 1, PWM 1.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 3.
Port 0, Bit 5, PWM 1.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Ground connection.
I
2
C Clock.
I
2
C Data.
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
Ground connection.
Port 2, Bit 2, PWM 0, E
2
Write Disable.
Port 2, Bit 1, PWM 0, Address 2.
Port 2, Bit 0, PWM 2, Address 3.
Active high external reset with internal pull
down.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 0, Address 6.
Port 1, Bit 4, PWM 2.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 0.
Port 1, Bit 0, PWM 2.
Supply voltage.
Figure 2. CY8C9520A 28-Pin Device
GPort0_Bit0_PWM3
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
Vss
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
GPort1_Bit0_PWM2
GPort1_Bit1_PWM0
GPort1_Bit2_PWM2
GPort1_Bit3_PWM0
GPort1_Bit4_PWM2
GPort1_Bit5_PWM0/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
XRES
GPort2_Bit0_PWM2/A3
GPort2_Bit1_PWM0/A2
INT
GPort2_Bit2_PWM0/WD
Document Number: 38-12036 Rev. *E
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