SB-36310CX
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has...
®
FOUR CHANNEL PC/104 COMPATIBLE
SYNCHRO/RESOLVER-TO-DIGITAL CARD
FEATURES
•
Contains up to Four Independent
Converter Channels
•
Accepts Synchro or Resolver Inputs
•
Accuracy to ±1 min.
•
Synthesized Reference
•
Velocity Output Signal for Each
Channel
•
Software Programmable Resolution
and Bandwidth
•
Jumper Programmable Reference
Voltage Inputs
•
Discrete I/O for External Control
Functions
DESCRIPTION
The SB-36310CX is a versatile, PC/104 card which contains one to
four channels of fully independent Synchro-to-Digital or Resolver-to-
Digital (S/R-D) conversion. For each channel the conversion process
is implemented using a DDC RDC-19222S 16-bit monolithic convert-
er and a thin-film resistor network.
Each converter can be configured for a 11.8 V line-to-line
synchro/resolver, 90 V line-to-line synchro, or 2 V sin/cos signal input,
and 10-, 12-, 14-, or 16-bit resolution. The user is provided with two
operating frequency ranges. The low bandwidth card operates from
47 Hz to 5 kHz and is software programmable for bandwidths of 15
Hz or 45 Hz. The high bandwidth card operates from 360 Hz to 5 kHz
and is software programmable for bandwidths of 80 Hz or 300 Hz.
Each channel provides a separate reference input which is jumper
programmable to accept either a 26 V or a 115 V signal. A synthesized
reference and accuracy to ±1 minute is standard.
In addition to the angular position data, each channel provides a ±4 V
Velocity Output Signal, and 16-bit Discrete I/O configured with 8 bits
of input and 8 bits of output which are available for user defined func-
tions. Demo software including source code is supplied with the card.
APPLICATIONS
The SB-36310CX is designed for modern, high-performance industrial
and military control systems. Typical applications include motor control,
machine tool control, robotic, antenna and process control systems.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
© 2000 Data Device Corporation
Data Device Corporation
www.ddc-web.com
PC/104 BUS
INTERFACE
DATA
S1
BIT
INH
STATUS
REGISTER
S2
RESOLVER
TO
DIGITAL
CONVERTER
#1
BANDWIDTH
RESOLUTION
EM, EL
CONTROL
REGISTERS
S3
Solid State
Thin-Film Input
S4
REF
2
ADDRESS
DECODER
ADDRESS
S1
I/O READ
I/O WRITE
I/O ENABLE
DISCRETE I/O
RESET
S2
RESOLVER
TO
DIGITAL
CONVERTER
#4
S3
Solid State
Thin-Film Input
S4
REF
DISCRETE DISCRETE
OUTPUT
INPUT
SB-36310CX
G-05/05-0
FIGURE 1. SB-36310CX BLOCK DIAGRAM
TABLE 1. SB-36310CX SPECIFICATIONS
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; and 10% signal amplitude and 10%
harmonic distortion.
PARAMETER
RESOLUTION
UNIT
Bits
Min.
+1LSB
LSB
LSB
VALUE
10, 12, 14, or 16
1
2
2
2
for
for
for
for
input
input
input
input
option
option
option
option
4
3
2
1
INTRODUCTION
Each of the four converter channels can be independently soft-
ware programmed for bandwidth and resolution. The reference
input voltage range is also selectable via jumpers for each chan-
nel. Two frequency ranges are available (see the Accuracy /
Bandwidth ordering options -XX5 or -XX6 in the Ordering
Information section):
• For the frequency ranges of 47 Hz to 5 kHz the
software programmability provides for bandwidths of 15 Hz
and 45 Hz (Low bandwidth option -XX6). (see TABLE 2B)
• For the 360 Hz to 5 kHz frequency range the corresponding
bandwidths are 80 Hz and 300 Hz (High bandwidth option -
XX5). (see TABLE 2A).
The heart of each channel is DDC’s RDC-19222S Monolithic
Resolver-to-Digital converter series. The RDC-19222S converter
adds a synthesized Reference to reduce positional error caused
by Rotor-to-Stator phase shift and offers an accuracy option
of ±1 minute.
For technical information on the RDC-19222S converter consult
the respective data sheet. Each channel of the SB-36310CX can
be configured to accept 11.8 V
L-L
synchro/resolver, 90 V
L-L
syn-
chro, or 2V single ended (sin/cos) signals. The synchro or
resolver format is programmable by placing the resistor network
into one of two socket locations for each individual channel, and
is preconfigured at the factory.
NOTE: Unused channels do not require an RDC-19222S
converter or thin-film resistor network.
The reference input can be configured to accept 115 Vrms or
26 Vrms reference input, based on the setting of two jumpers
(See FIGURE 6). In addition, each channel’s resolution can be
software programmed for 10, 12, 14, or 16 bits. (See the
RDC-19222S Series data sheet, TABLE 1).
The angular data for each channel can be Inhibited (frozen) or
Enabled. Each channel can be Inhibited (INH) independently or
all installed channels can be Inhibited simultaneously and read
in sequence. A block diagram of the SB-36310CX is shown in
FIGURE 1.
WARNING !
To prevent personal injury always remove the I/O
CONNECTOR prior to servicing the SB-36310CX.
The I/O connector may contain HIGH VOLTAGES
(115V and 90V).
These voltages may be present
even if the power to the computer is turned OFF.
ACCURACY (NOTE 1,3)
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT (RH, RL)
Type
Voltage Range
Input Impedance
single ended
differential
Frequency Range Low BW
High BW
SIGNAL INPUT
CHARACTERISTICS
Synchro
Zin line-to-line
Zin line-to-ground
Resolver Input (L-L)
Zin single ended
Zin differential
Common Mode Voltage
DYNAMIC CHARACTERISTICS
ANALOG OUTPUTS
Velocity (VEL)
POWER SUPPLY
Nominal Voltage
Typical Current Draw
no converters
4 converters
TEMPERATURE RANGE
Operation (Option -3)
(Option -2)
Storage
(Option -3)
(Option -2)
DIMENSIONS
Size
1 max.
1 max.
Each Channel
Differential
Vrms
Ohms
Ohms
Hz
Hz
2 - 28
90k min.
180k min.
10 - 130
450k min.
900k min.
47 - 5k
360 - 5k
V
Ohms
Ohms
V
Ohms
Ohms
V max.
N/A
N/A
N/A
2
10M min. ||
10 pF
N/A
N/A
11.8
52k
35k
11.8
70k
140k
30
90
195k
130k
90
260k
520k
180
See TABLES 2A & 2B
See TABLE 3
V
mA
mA
°C
°C
°C
°C
+5
150
200
+12 (Note 2)
---
---
0 to +70
-40 to +85
0 to +80
-55 to +100
-12
5
60
inches
(cm)
3.78 x 4.36 x 0.932 max.
(9.60 x 11.1 x 2.37)
NOTES:
1. Includes 1 bit of jitter in 16-bit mode.
2. The +12V power supply is only used for transient protection of the discrete I/O.
There is a 33 V zener diode between the common inputs of the discrete and
the +12V power supply.
3. Input options 1, 2, 3 can be screened to 1 minute accuracy on special
requests.
Data Device Corporation
www.ddc-web.com
3
SB-36310CX
G-05/05-0
TABLE 2A. DYNAMIC CHARACTERISTICS
HIGH BANDWIDTH CARD
PARAMETER
Resolution
Tracking Rate
UNIT
HIGH RANGE
12*
288
300
506k
1.7
296k
711.7
355.8
44.6k
12.9
14**
72
300
506k
1.7
296k
711.7
355.8
11.1k
20.9
16**
18
300
506k
1.7
296k
711.7
355.8
2.8k
43.0
bits
10*
rps min. 1152
(typ)
BW (Closed Loop)
Hz nom. 300
Ka
1/sec
2
506k
A1
1/sec
1.7
A2
1/sec
296k
A
1/sec
711.7
B
1/sec
355.8
Acceleration (1 LSB lag) deg/sec 178.3k
Settling Time
ms typ. 10.2
(179 deg. step)
PARAMETER
Resolution
Tracking Rate
UNIT
10*
320
80
31.6k
0.44
81.6k
177.7
88.9
11.1k
40.9
bits
rps min.
(typ)
BW (Closed Loop)
Hz nom.
Ka
1/sec
2
1/sec
A1
1/sec
A2
1/sec
A
1/sec
B
Acceleration (1 LSB lag) deg/sec
ms typ.
Settling Time
(179 deg. step)
*
TABLE 3. VELOCITY CHARACTERISTICS
PARAMETER
Polarity
Voltage Range
Voltage Scaling
(resolution
dependent)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
UNIT
V
TYPICAL
4.0
Tracking Rate
Typical (See TABLES 2A & 2B)
4
10
100
1
0.5
5
15
20 (max.)
200 (max.)
2 (max.)
1 (max.)
15 (max.)
30 (max.)
10 (min.)
MAX./MIN.
RPS/V
%
PPM / deg C
%
% output
mV
µV / deg C
k Ohms
LOW RANGE
12*
80
80
31.6k
0.44
81.6k
177.7
88.9
2.8k
51.2
14**
20
80
31.6k
0.44
81.6k
177.7
88.9
695
81.1
16**
5
80
31.6k
0.44
81.6k
177.7
88.9
173.7
161
TRANSFER FUNCTION
The dynamic performance of the converter can be determined
from its Transfer Function (Refer to FIGURES 2 and 3). The open
loop transfer function is as follows:
A2
Open Loop Transfer Function =
S2
(
S + 1
)
B
S
(
10B + 1
)
Exceeds tracking rate to bandwidth ratio. Selecting a bandwidth that is too
low relative to the maximum application tracking rate can create a spin-around
condition in which the converter never settles (particularly during initial power
-up.) (Refer to “Tracking/BW Relationship” table in RDC-19222S data sheet.)
** Converters may jitter at carrier frequencies < 1.5 kHz
where A is the gain coefficient and A2 = A
1
A
2
and B is the frequency of lead compensation
A
1
Error Processor, G1 Gain =
TABLE 2B. DYNAMIC CHARACTERISTICS
LOW BANDWIDTH CARD
PARAMETER
Resolution
Tracking Rate
UNIT
HIGH RANGE
12*
40
45
10.13k
0.25
41.03k
100
50
891.4
92
14**
10
45
10.13k
0.25
41.03k
100
50
222.9
149
16**
2.5
45
10.13k
0.25
41.03k
100
50
55.7
308
bits
10*
rps min. 160
(typ)
BW (Closed Loop)
Hz nom.
45
Ka
1/sec
2
10.13k
1/sec
A1
0.25
1/sec 41.03k
A2
1/sec
A
100
1/sec
B
50
Acceleration (1 LSB lag) deg/sec 3.57k
ms typ.
Settling Time
73
(179 deg. step)
UNIT
bits
10*
rps min.
32
(typ)
BW (Closed Loop)
Hz nom.
15
Ka
1/sec
2
1.11k
1/sec
A1
0.14
1/sec
A2
8.16k
1/sec
A
33.3
1/sec
B
16.7
Acceleration (1 LSB lag) deg/sec 390.83
ms typ.
Settling Time
226
(179 deg. step)
*
(
S + 1
)
B
S
S
(
10B + 1
)
VCO, G2 = A
2
/ S
RB C
BW
VEL
C
BW
/10
RS
-VSUM
VEL
-VCO
50 pf
C
VCO
CT
RESOLVER
INPUT
(θ)
+
GAIN
DEMOD
1
C
S
F
S
11 mV/LSB
±1.25 V
THRESHOLD
R
V
R1
VCO
-
16 BIT
UP/DOWN
COUNTER
H=1
PARAMETER
Resolution
Tracking Rate
LOW RANGE
12*
14**
8
2
15
1.11k
0.14
8.16k
33.3
16.7
97.71
302
15
1.11k
0.14
8.16k
33.3
16.7
24.43
549
DIGITAL
OUTPUT
(φ)
16**
0.5
15
1.11k
0.14
8.16k
33.3
16.7
6.11
1325
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S S +1
10B
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
Exceeds tracking rate to bandwidth ratio. Selecting a bandwidth that is too
low relative to the maximum application tracking rate can create a spin-around
condition in which the converter never settles (particularly during initial power
-up.) (Refer to “Tracking/BW Relationship” table in RDC-19222S data sheet.)
** Converters may jitter at carrier frequencies < 225 Hz
H=1
FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
SB-36310CX
G-05/05-0
Data Device Corporation
www.ddc-web.com
4
SYNCHRO/RESOLVER INPUT SETTING
The input configuration for each channel on the SB-36310CX is
determined by the thin-film resistor network position on the
board. Each channel has two possible positions for the thin-film
resistor network to be installed on the board. When viewing the
card with the J1/P1, J2/P2 connectors facing down, the left hand
socket is for synchro input and the right hand socket is for
resolver input (refer to FIGURE 4).
NOTE: Channels 1, 2, and 3 have two sockets offset by
0.1”, and channel 4 has two sockets in line.
BASE ADDRESS SETTING
The Base Address of the SB-36310CX is preset at the factory to
HEX address 0330h as shown in FIGURE 5. The user may
choose from 0000h to 0FF0h in 10 HEX increments.
I/O Connector
8 Bit Input
8 Bit Output
26V
(CH4)
115V
26V
(CH3)
115V
RDC-19222S
RDC-19222S
(CH2)
26V
J4
115V
J3
RDC-19222S
8
The signal amplitude is determined by the type of thin-film resis-
tor network purchased for each channel. The DDC-49530 will
accept 11.8 V
L-L
, the DDC-49590 will accept 90 V
L-L
, and the
DDC-55688 will accept 2 V sin/cos inputs. For more information
about the DDC-49530 and the DDC-49590 please refer to the
Thin-Film Resistor Network data sheet. The DDC-55688 can
only be placed in the resolver socket.
NOTE: Unused Channels do not require a thin-film resistor
network.
Channel 4
Resolver
Synchro
(CH1)
26V
J5
1
115V
RDC-19222S
J6
J1/P1
J2/P2
MSB
A15
LSB
A0
1 2 3 4 5 6 7 8
J5
edge of card)
(viewed from
0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 Binary
0
3
3
0
Hex
FIGURE 5. ADDRESS DECODING
REFERENCE INPUT
Ch. 4
Channels 1, 2, and 3
Synchro
Resolver
RDC-19222S
RDC-19222S
Ch. 3
Ch. 2
RDC-19222S
An excitation or reference on the primary of the synchro or
resolver is also needed to demodulate the synchro/resolver
signals. The SB-36310CX has resistors that attenuate the
reference to a level that is acceptable for the RDC-19222
converter.
For a 2 Vrms to 28 Vrms reference the jumpers should be set for
a 26 V nominal reference. For a 10 Vrms to 130 Vrms reference
the jumpers should be set for a 115 V nominal reference. Refer
to FIGURE 6 to set the jumpers.
26 V
115 V
Ch.1
RDC-19222S
Viewing card with J1/P1, J2/P2 pointing down
FIGURE 4. SYNCHRO/RESOLVER INPUT USING THIN-
FILM RESISTOR NETWORKS
Viewing card with
J1/P1, J2/P2
pointing down.
REGISTER ADDRESSING
(CH4)
26V
26V
(CH3)
RDC-19222S
RDC-19222S
115V
115V
The SB-36310CX is addressed in typical Base Address and
Offset fashion. Each read/write register is 16 bits wide.
The Memory Map of the I/O registers is detailed in TABLE 4.
(CH2)
26V
J4
115V
J3
RDC-19222S
J5
TABLE 4. SB-36310CX MEMORY MAP
HEX OFFSET
00
02
04
06
08
READ/WRITE
Channel Select and Inhibit (Read/Write)
Bandwidth and Resolution (Read/Write)
Status Register (Read Only)
8 Bit Digital I/O (Read/Write)
Angle Data (Read Only)
(CH1)
26V
115V
RDC-19222S
J6
J1/P1
J2/P2
Factory
Use
Only
FIGURE 6. REFERENCE CONFIGURATION
5
SB-36310CX
G-05/05-0
Data Device Corporation
www.ddc-web.com
单片机
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