3.3 VOLT CMOS SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
Integrated Device Technology, Inc.
PRELIMINARY
IDT72V255
IDT72V265
FEATURES:
• 3.3 Volt operation saves 60 percent power compared to
the functionally compatible 5 Volt 72255/65 Family
• 8,192 x 18-bit storage capacity (IDT72V255)
• 16,384 x 18-bit storage capacity (IDT72V265)
• 15ns read/write cycle time (10ns access time)
• Retransmit Capability
• Auto power down reduces power consumption
• Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
• Empty, Full and Half-full flags signal FIFO status
• Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using
EF
and
FF
flags) or
First Word Fall Through timing (using
OR
and
IR
flags)
• Easily expandable in depth and width
• Independent read and write clocks (permit simultaneous
reading and writing with one clock signal)
• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) the 68-pin Pin
Grid Array (PGA)
• Output enable puts data outputs into high impedance
• High-performance submicron CMOS technology
DESCRIPTION:
The 72V255/72V265 are functionally compatible versions
of the 72255/65 designed to run off a 3.3V supply for excep-
tionally low power consumption. The IDT72V255/72V265 are
monolithic, CMOS, high capacity, high speed, First-In, First-
Out (FIFO) memories with clocked read and write controls.
These FIFOs are applicable for a wide variety of data buffering
needs, such as optical disk controllers, local area networks
(LANs), and inter-processor communication.
Both FIFOs have an 18-bit input port (Dn) and an 18-bit
output port (Qn). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (
WEN
). Data is
written into the synchronous FIFO on every clock when
WEN
is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (REN). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D0-D17
LD SEN
•
•
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
•
•
RAM ARRAY
8,192 x 18
16,384 x 18
•
•
FLAG
LOGIC
FF
/
IR
PAF
EF
/
OR
PAE
HF
FWFT/SI
READ POINTER
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MRS
PRS
FS
RESET LOGIC
•
•
•
RCLK
REN
TIMING
OE
Q0-Q17
3478 drw 01
SuperSync FIFO and SyncFIFO are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology
DECEMBER 1995
DSC-3478/-
5.04
1
IDT72V255/72V265 3.3Volt SyncFIFO™
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
enable pin (
OE
) is provided on the read port for three-state
control of the outputs.
The IDT72V255/72V265 have two modes of operation: In
the
IDT Standard Mode,
the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the
First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The IDT72V255/72V265 FIFOs have five flag functions,
EF
/
OR
(Empty Flag or Output Ready),
FF
/
IR
(Full Flag or Input
Ready), and HF (Half-full Flag). The
EF
and
FF
functions are
selected in the IDT Standard Mode.
The
IR
and
OR
functions are selected in the First Word Fall
Through Mode.
IR
indicates that the FIFO has free space to
receive data.
OR
indicates that data contained in the FIFO is
available for reading.
HF is a flag whose threshold is fixed at the half-way point
in memory. This flag can always be used irrespective of
mode.
PAE
,
PAF
can be programmed independently to any point
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that
PAE
can be set at
127 or 1023 locations from the empty boundary and the
PAF
threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with
LD
during Master
Reset.
In the serial method,
SEN
together with
LD
are used to load
the offset registers via the Serial Input (SI). In the parallel
method,
WEN
together with
LD
can be used to load the offset
registers via Dn. REN together with
LD
can be used to read
the offsets in parallel from Qn regardless of whether serial or
parallel offset loading is selected.
During Master Reset (
MRS
), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The
LD
pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
PAE
EF
/
OR
WCLK
GND
FF
/
IR
PRS
MRS
LD
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
FS
V
CC
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
REN
RT
OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
RCLK
PIN CONFIGURATIONS
FWFT/SI
PAF
HF
PN64-1
PP64-1
Q17
Q16
GND
Q15
Q14
V
CC
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D6
D5
D4
D3
D2
D1
D0
GND
Q0
Q1
GND
Q2
Q3
V
CC
Q4
Q5
3478 drw 02
TQFP
STQFP
TOP VIEW
5.04
2
IDT72V255/72V265 3.3Volt SyncFIFO™
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
parallel programming. The flags are updated accordingly.
The Partial Reset (
PRS
) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly.
PRS
is
useful for resetting a device in mid-operation, when repro-
gramming offset registers may not be convenient.
The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when
RT
is LOW. This feature is convenient for
sending the same data more than once.
If, at any time, the FIFO is not actively performing a
function, the chip will automatically power down. This occurs
if neither a read nor a write occurs within 10 cycles of the faster
clock, RCLK or WCLK. During the Power Down state, supply
current consumption (ICC2) is at a minimum. Initiating any
operation (by activating control inputs) will immediately take
the device out of the Power Down state.
The IDT72V255/72V265 are depth expandable. The addi-
tion of external components is unnecessary. The
IR
and
OR
functions, together with REN and
WEN
, are used to extend the
total FIFO memory capacity.
The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency
The IDT72V255/72V265 is fabricated using IDT’s high
speed submicron CMOS technology.
PIN CONFIGURATIONS (CONT.)
11
10
09
08
07
06
05
04
03
02
01
A
Q
6
Q
8
Q
10
Q
11
DNC
GND
Q
7
Q
9
GND
Q
5
Q
4
V
CC
Q
3
Q
2
GND
Q
1
Q
0
GND
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
9
D
11
D
13
D
7
D
8
D
10
D
12
D
14
D
16
GND
FS
Q
13
Q
14
GND
Q
17
Q
12
V
CC
G68-1
D
15
D
17
Pin 1 Designator
Q
15
Q
16
V
CC
SEN
REN
RCLK
DNC
OE
RT
B
GND
PAE
V
CC
E
HF
PAF
F
FF
/
IR
GND
G
DNC
FWFT/
SI
LD
WCLK
WEN
EF
/
OR
D
MRS PRS
J
K
3478 drw 03
C
H
L
PGA
TOP VIEW
NOTES
:
1. DNC = Do not connect
5.04
3
IDT72V255/72V265 3.3Volt SyncFIFO™
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D
0
–D
17
Name
Data Inputs
Master Reset
I/O
I
I
Description
Data inputs for a 18-bit bus.
MRS
PRS
RT
FWFT/SI
WCLK
MRS
initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
Partial Reset
I
PRS
initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
Retransmit
First Word Fall
Through/Serial In
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
I
I
I
I
I
Allows data to be resent starting with the first location of FIFO memory.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by
WEN
, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers.
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN
, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
WEN
RCLK
REN
OE
SEN
LD
FS
FF
/
IR
REN
enables RCLK for reading data from the FIFO memory and offset registers.
OE
controls the output impedance of Q
n
SEN
enables serial loading of programmable flag offsets
During Master Reset,
LD
selects one of two partial flag default offsets (127 and
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
The FS setting optimizes data flow through the FIFO.
In the IDT Standard Mode, the
FF
function is selected.
FF
indicates whether or
not the FIFO memory is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard Mode, the
EF
function is selected.
EF
indicates whether or
not the FIFO memory is empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the outputs.
PAF
goes HIGH if the number of free locations in the FIFO memory is more than
offset m which is stored in the Full Offset register.
PAF
goes LOW if the num-
ber of free locations in the FIFO memory is less than m.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n
which is stored in the Empty Offset register.
PAE
goes HIGH if the number of
words in the FIFO memory is greater than offset n.
HF
indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 18-bit bus.
+3.3 Volt power supply pins.
Ground pins.
3478 tbl 01
Frequency Select
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost Full Flag
Programmable
Almost Empty
Flag
Half-full Flag
Data Outputs
Power
Ground
I
O
EF
/
OR
PAF
PAE
HF
Q
0
–Q
17
V
CC
GND
O
O
O
O
O
5.04
4
IDT72V255/72V265 3.3Volt SyncFIFO™
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
NOTE:
Rating
Commercial
MIilitary
–0.5 to +7.0
–55 to +125
–65 to +135
–65 to +155
50
Unit
V
°C
°C
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CCM
V
CCC
GND
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Min. Typ.
3.0 3.3
3.0
0
2.0
2.0
—
3.3
0
—
—
—
Max.
3.6
3.6
0
Vcc+0.5
Vcc+0.5
0.8
Unit
V
V
V
V
V
V
3478 tbl 03
Terminal Voltage
–0.5 to +7.0
with respect to GND
Operating
Temperature
0 to +70
Temperature Under –55 to +125
Bias
Storage
Temperature
DC Output Current
–55 to +125
50
°C
mA
V
IH
V
IH
V
IL(1)
NOTE:
3478 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V
±
0.3V, T
A
= 0°C to +70°C; Military: V
CC
= 3.3V
±
0.3V, T
A
= –55°C to +125°C)
DT72V255L
IDT72V265L
Commercial
t
CLK
= 15, 20ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
GND + 0.2V, RCLK and WCLK are free-running)
NOTES
:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
= V
IH
3. Tested at f = 20 MHz with outputs unloaded.
3478 tbl 04
IDT72V255L
IDT72V265L
Military
t
CLK
= 20, 25ns
Min.
–10
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
10
10
—
0.4
100
10
Unit
µA
µA
V
V
mA
mA
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
100
10
I
CC2(3,4)
Power Down Current (All inputs = V
CC
- 0.2V or
4. No data written or read for more than 10 cycles
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
10
10
Unit
pF
pF
3478 tbl 05
NOTES:
1. With output deselected, (
OE
=HIGH).
2. Characterized values, not currently tested.
5.04
5
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