DATA SHEET
µ
PD178023,178024
8-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD178023, 178024 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning
systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit.
In addition, three serial interfaces, I
2
C bus (IIC0), three-wire (SIO3), and UART are provided.
Moreover, a flash memory model, the
µ
PD178F124, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also available.
For the detailed functional description, refer to the following User’s Manuals:
µ
PD178024 Subseries User’s Manual
: U13915E
78K/0 Series User’s Manual - Instruction : U12326E
FEATURES
•
High-capacity ROM and RAM
Item
Part Number
Program Memory (ROM)
Data Memory
Internal high-speed RAM
24K bytes
32K bytes
1024 bytes
µ
PD178023
µ
PD178024
•
Instruction cycle:
f
X
= 4.5 MHz)
0.45/0.89/1.78/3.56/7.11
µ
s (with crystal resonator of
•
Hardware for PLL frequency synthesizer
•
Vectored interrupt sources:
•
Supply voltage
phase comparator, charge pump
17
Dual modulus prescaler, programmable divider,
•
Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (I
2
C bus and UART mode), timers, frequency
:V
DD
= 4.5 to 5.5 V (during PLL and CPU
operations)
counter, power-ON clear circuit
:V
DD
= 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U14126EJ2V0DS00 (2nd edition)
Date Published September 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
µ
PD178023, 178024
FUNCTIONAL OUTLINE
(1/2)
Item
Internal
memory
ROM
24 Kbytes
(Mask ROM)
1024 bytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
0.45
µ
s/0.89
µ
s/1.78
µ
s/3.56
µ
s/7.11
µ
s (with crystal resonator of f
X
= 4.5 MHz)
•
•
•
•
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
: 62 pins
: 53 pins
: 6 pins
µ
PD178023
32 Kbytes
(Mask ROM)
µ
PD178024
High-speed RAM
General-purpose register
Minimum instruction execution time
Instruction set
I/O port
Total
• CMOS I/O
• CMOS input
• N-ch open-drain output : 3 pins
A/D converter
Serial interface
8-bit resolution
×
6 channels (V
DD
= 3.5 to 5.5 V)
• I
2
C bus mode
Note
: 1 channel
• 3-wire mode
: 1 channel
• UART mode
: 1 channel
• Basic timer (timer carry FF (10 Hz)) : 1 channel
• 8-bit timer/event counter
: 2 channels
• Watchdog timer
Buzzer output
Vectored
interrupt
source
Maskable
: 1 channel
Timer
1 channel (1 kHz, 1.5 kHz, 3 kHz, 4 kHz)
Internal : 11
External: 5
Internal: 1
1
2 types
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOL and VCOH pins)
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Error out output: 2 pins
Unlock detectable in software
Non-maskable
Software
PLL
frequency
synthesizer
Division mode
Reference frequency
Charge pump
Phase comparator
Note
When the I
2
C bus mode is used (including when the mode is implemented in software without using the
peripheral hardware), consult NEC when ordering a mask.
4
Data Sheet U14126EJ2V0DS00
µ
PD178023, 178024
(2/2)
Item
Frequency counter
µ
PD178023
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
• Reset by RESET pin
• Internal reset by watchdog timer
µ
PD178024
Reset
• Reset by power-ON clear circuit
• Detection of less than 4.5 V
Note
(Reset does not occur, however.)
• Detection of less than 3.5 V
Note
(during CPU operation)
• Detection of less than 2.3 V
Note
(in STOP mode)
Supply voltage
• V
DD
= 4.5 to 5.5 V (during CPU, PLL operation)
• V
DD
= 3.5 to 5.5 V (during CPU operation)
• 80-pin plastic QFP (14
×
20)
• 80-pin plastic QFP (14
×
14)
Package
Note
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U14126EJ2V0DS00
5
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