Integrated
Circuit
Systems, Inc.
ICS8304-01
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL I
NVERTING
F
ANOUT
B
UFFER
F
EATURES
•
4 LVCMOS / LVTTL outputs
•
LVCMOS/LVTTL clock input
•
Maximum output frequency: 166MHz
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 600ps (maximum)
•
Small 8 lead SOIC package saves board space
•
3.3V input, outputs may be either 3.3V or 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS8304-01 is a low skew, 1-to-4 Invert-
ing Fanout B u f fe r a n d a m e m b e r o f t h e
HiPerClockS™
HiPerClock S ™ family of High Perfor mance
Clock Solutions from ICS. The ICS8304-01
is characterized at full 3.3V for input V
DD
, and
mixed 3.3V and 2.5V for output operating supply modes
(V
DDO
). Guaranteed output and par t-to-par t skew char-
acteristics make the ICS8304-01 ideal for those clock
distribution applications demanding well defined per-
for mance and repeatability.
ICS
B
LOCK
D
IAGRAM
nQ0
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
nQ3
nQ2
nQ1
nQ0
nQ1
CLK
nQ2
ICS8304-01
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
nQ3
8304AM-01
www.icst.com/products/hiperclocks.html
1
REV. D MAY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS8304-01
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL I
NVERTING
F
ANOUT
B
UFFER
Type
Power
Power
Input
Power
Output
Output
Output
Output
Description
Output supply pin.
Core supply pin.
Pulldown LVCMOS / LVTTL clock input.
Power supply ground.
Inver ted version of clock input. LVCMOS / LVTTL interface levels.
Inver ted version of clock input. LVCMOS / LVTTL interface levels.
Inver ted version of clock input. LVCMOS / LVTTL interface levels.
Inver ted version of clock input. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
Name
V
DDO
V
DD
CLK
GN D
nQ 0
nQ 1
nQ 2
nQ 3
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
V
DD
, V
DDO
= 3.465V
51
7
15
Maximum
Units
pF
pF
kΩ
Ω
8304AM-01
www.icst.com/products/hiperclocks.html
2
REV. D MAY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS8304-01
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL I
NVERTING
F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
DD
Outputs, V
DDO
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
X
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
15
8
Units
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information Section",
"3.3V Output Load Test Circuit".
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
2.3
Test Conditions
Minimum
Typical
Maximum
166
3.5
50
600
500
500
60
Units
MHz
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
166MHz
40
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output. Measured from the rising edge of
the input to the falling edge of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM-01
www.icst.com/products/hiperclocks.html
3
REV. D MAY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS8304-01
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL I
NVERTING
F
ANOUT
B
UFFER
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
15
8
Units
V
V
mA
mA
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
T
ABLE
3D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
2.1
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information Section,
"3.3V/2.5V Output Load Test Circuit".
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
2.5
Test Conditions
Minimum
Typical
Maximum
166
3.6
50
600
500
500
60
Units
MHz
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
166MHz
40
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output. Measured from the rising edge of
the input to the falling edge of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM-01
www.icst.com/products/hiperclocks.html
4
REV. D MAY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS8304-01
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL I
NVERTING
F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
V
DD
,
V
DDO
SCOPE
Qx
V
DD
V
DDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
V
DDO
2
V
DDO
2
-1.65V±5%
-1.25V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
V
nQx
2
DDO
V
DDO
PART 1
2
V
nQy
DDO
V
DDO
2
tsk(o)
nQy
PART 2
2
tsk(pp)
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
70%
30%
t
R
70%
CLK
V
DD
2
V
DDO
2
t
PD
Clock
Outputs
30%
t
F
nQ0:nQ3
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
nQ0:nQ3
V
DDO
t
PW
t
PERIOD
2
O
UTPUT
D
UTY
C
YLE
/P
ULSE
W
IDTH
/P
ERIOD
8304AM-01
www.icst.com/products/hiperclocks.html
5
REV. D MAY 23, 2005
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
