E2O0020-27-X3
¡ Semiconductor
MSM82C55A-2RS/GS/VJS
¡ Semiconductor
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
This version: Jan. 1998
MSM82C55A-2RS/GS/VJS
Previous version: Aug. 1996
GENERAL DESCRIPTION
The MSM82C55A-2 is a programmable universal I/O interface device which operates as high
speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best
fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU.
This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are
TTL interface compatible.
FEATURES
• High speed and low power consumption due to 3m silicon gate CMOS technology
• 3 V to 6 V single power supply
• Full static operation
• Programmable 24-bit I/O ports
• Bidirectional bus operation (Port A)
• Bit set/reset function (Port C)
• TTL compatible
• Compatible with 8255A-5
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K)
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¡ Semiconductor
MSM82C55A-2RS/GS/VJS
AC CHARACTERISTICS
Parameter
Setup Time of Address to the Falling Edge of
RD
Hold Time of Address to the Rising Edge of
RD
RD
Pulse Width
Delay Time from the Falling Edge of
RD
to the Output of
Defined Data
Delay Time from the Rising Edge of
RD
to the Floating of
Data Bus
Time from the Rising Edge of
RD
or
WR
to the Next Falling
Edge of
RD
or
WR
Setup Time of Address before the Falling Edge of
WR
Hold Time of Address after the Rising Edge of
WR
WR
Pulse Width
Setup Time of Bus Data before the Rising Edge of
WR
Hold Time of Bus Data after the Rising Edge of
WR
Delay Time from the rising Edge of
WR
to the Output of
Defined Data
Setup Time of Port Data before the Falling Edge of
RD
Hold Time of Port Data after the Rising Edge of
RD
ACK
Pulse Width
STB
Pulse Width
Setup Time of Port Data before the rising Edge of
STB
Hold Time of Port Bus Data after the rising Edge of
STB
Delay Time from the Falling Edge of
ACK
to the Output of
Defined Data
Delay Time from the Rising Edge of
ACK
to the Floating of
Port (Port A in Mode 2)
Delay Time from the Rising Edge of
WR
to the Falling Edge of
OBF
Delay Time from the Falling Edge of ACK to the Rising Edge of
OBF
Delay Time from the Falling Edge of STB to the Rising Edge of
IBF
Delay Time from the Rising Edge of
RD
to the Falling Edge of
IBF
Delay Time from the the Falling Edge of
RD
to the Falling Edge
of INTR
Delay Time from the Rising Edge of
STB
to the Rising Edge of
INTR
Delay Time from the Rising Edge of
ACK
to the Rising Edge of
INTR
Delay Time from the Falling Edge of
WR
to the Falling Edge of
INTR
(V
CC
= 4.5 V to 5.5 V, Ta = –40 to +85°C)
MSM82C55A-2
Symbol
Unit Remarks
Min.
Max.
t
AR
t
RA
t
RR
t
RD
t
DF
t
RV
t
AW
t
WA
t
WW
t
DW
t
WD
t
WB
t
IR
t
HR
t
AK
t
ST
t
PS
t
PH
t
AD
t
KD
t
WOB
t
AOB
t
SIB
t
RIB
t
RIT
t
SIT
t
AIT
t
WIT
20
0
100
—
10
200
0
20
150
50
30
—
20
10
100
100
20
50
—
20
—
—
—
—
—
—
—
—
—
—
—
120
75
—
—
—
—
—
—
200
—
—
—
—
—
—
150
250
150
150
150
150
200
150
150
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load
150 pF
Note: Timing measured at V
L
= 0.8 V and V
H
= 2.2 V for both inputs and outputs.
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