3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING 16,384 X 16,384 CHANNELS
IDT72V73263
FEATURES:
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Up to 64 serial input and output streams
Maximum 16,384 x 16,384 channel non-blocking switching
Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,
16.384Mb/s or 32.768Mb/s
Rate matching capability: rate selectable on both RX and TX
in eight groups of 8 streams
Optional Output Enable Indication Pins for external driver
High-Z control
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Enhanced Block programming capabilities
TX/RX Internal Bypass
Automatic identification of ST-BUS
and GCI serial streams
Per-stream frame delay offset programming
Per-channel High-Impedance output control
Per-channel processor mode to allow microprocessor writes to TX
streams
Bit Error Rate Testing (BERT) for testing
Direct microprocessor access to all internal memories
Selectable Synchronous and Asynchronous Microprocessor
bus timing modes
IEEE-1149.1 (JTAG) Test Port
Available in 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)
Operating Temperature Range -40°C to +85°C
°
°
The IDT72V73263 has a non-blocking switch capacity of 16,384 x 16,384
channels at 32.768Mb/s. With 64 inputs and 64 outputs, programmable per
stream control, and a variety of operating modes the IDT72V73263 is
designed for the TDM time slot interchange function in either voice or data
applications.
Some of the main features of the IDT72V73263 are LOW power 3.3 Volt
operation, automatic ST-BUS
®
/GCI sensing, memory block programming,
simple microprocessor interface , JTAG Test Access Port (TAP) and per
stream programmable input offset delay, variable or constant throughput
modes, output enable and processor mode, BER testing, bypass mode, and
advanced block programming.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
September 2007
DSC-6160/4
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A1 BALL PAD CORNER
A
C32i
R ESET
ODE
RX1
RX4
TX0
TX4
TX7
TX12/
OEI4
TX11/
OEI3
TX10/
OEI2
V
CC
TX15/
OEI7
TX14/
OEI6
TX13/
OEI5
V
CC
RX11
RX15
RX20
TX16
TX18
TX19
B
F32i
Vcc
RX0
RX2
RX5
TX1
TX5
TX8/
OEI0
TX9/
OEI1
V
CC
RX10
RX14
RX19
RX23
TX17
TX20
C
S/A
(1)
TMS
TDI
RX3
RX6
TX2
TX6
RX9
RX13
RX18
RX22
TX22
TX21
D
TDO
TCK
TR ST
DS
RX7
TX3
V
CC
RX8
RX12
RX17
RX21
TX24/
OEI16
TX26/
OEI18
TX29/
OEI21
RX25
TX23
E
CS
R/W
A0
A1
RX16
TX27/
OEI19
TX30/
OEI22
RX26
TX25/
OEI17
TX28/
OEI20
RX24
F
A2
A3
A4
A5
TX31/
OEI23
GND
GND
GND
GND
V
CC
G
A6
A7
A8
V
CC
H
A9
A10
A11
V
CC
GND
GND
GND
GND
V
CC
RX29
RX28
RX27
J
A14
A13
A12
V
CC
GND
GND
GND
GND
V
CC
RX30
RX31
RX32
K
D15
D TA/
BEH
D13
A15
V
CC
GND
GND
GND
GND
V
CC
RX33
RX34
RX35
L
D12
D14
BEL
RX36
RX37
RX38
RX39
M
D8
D9
D10
D11
TX32
TX33
TX34
TX35
N
D5
D6
D7
RX56
TX60/
OEI52
TX61/
OEI53
TX62/
OEI54
TX63/
OEI55
TX56/
OEI48
TX57/
OEI49
TX58/
OEI50
TX59/
OEI51
V
CC
V
CC
V
CC
V
CC
RX51
RX47
TX36
TX37
TX38
TX39
P
D3
D4
RX60
RX57
TX53
TX50
TX49
RX54
RX50
RX46
RX43
TX40/
OEI32
RX40
TX41/
OE33
TX46/
OEI38
TX45/
OEI37
TX42/
OEI34
TX43/
OEI35
TX44/
OEI36
R
D2
RX63
RX61
RX58
TX54
TX51
TX48
RX53
RX49
RX45
RX42
T
D1
D0
RX62
RX59
TX55
TX52
RX55
RX52
RX48
RX44
RX41
TX47/
OEI39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6160 drw03
NOTE:
1. S/A should be tied directly to VCC or GND for proper
operation.
PBGA: 1mm pitch, 17mm x 17mm (BB208-1 order code: BB)
TOP VIEW
2
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
A0-A15
BEL
C32i
CS
D0-15
DS
DTA/BEH
NAME
Address 0-15
Byte Enable LOW
Clock
Chip Select
Data Bus 0-15
Data Strobe
Data Transfer
Acknowledgment
Active LOW Output
I/O
I
I
I
I
I/O
I
D4
I/O
K2
PBGA
PIN NO.
*See PBGA
Table Below
L4
A1
E1
*See PBGA
Table Below
DESCRIPTION
These address lines access all internal memories.
In synchronous mode, this input will enable the lower byte (D0-7) on to the data bus.
Serial clock for shifting data in/out on the serial data streams. This input accepts a
32.768MHz clock.
Active LOW input used by a microprocessor to activate the microprocessor port of the
device.
These pins are the data bus of the microprocessor port.
This active LOW input works in conjunction with
CS
to enable the read and write
operations. This active LOW input sets the data bus lines (D0-D15).
In asynchronous mode this pin indicates that a data bus transfer is complete. When the
bus cycle ends,this pin drives HIGH and then High-Z allowing for faster bus cycles
with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level
when the pin is High-Z. When the device is in /Byte Enable HIGH synchronous
bus mode, this pin acts as an input and will enable the upper byte (D8-15) on to the
data bus.
This input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS
and GCI specifications.
Ground.
This is the output enable control for the TX serial outputs. When ODE input is LOW and
the OSB bit of the CR register is LOW, all TX outputs are in a High-Impedance state. If
this input is HIGH, the TX output drivers are enabled. However, each channel may
still be put into a High-Impedance state by using the per channel control bits in the
Connection Memory HIGH.
Serial data Input Stream. These streams may have data rates of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s, 16.384Mb/s, or 32.768Mb/s depending upon the selection in Receive
Data Rate Selection Register (RDRSR).
This input (active LOW) puts the device in its reset state that clears the device internal
counters, registers and brings TX0-63 and microport data outputs to a High-Impedance
state. The
RESET
pin must be held LOW for a minimum of 20ns to reset the device.
This input controls the direction of the data bus lines (D0-D15) during a microprocessor
access.
This input will select between asynchronous microprocessor bus timing and synchronous
microprocessor bus timing. In synchronous mode,
DTA/BEH
acts as the
BEH
input and is
used in conjunction with
BEL
to output data on the data bus. In asynchronous bus mode,
BEL
is tied LOW and
DTA/BEH
acts as the DTA, data bus acknowledgment output.
Provides the clock to the JTAG test logic.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH
by an internal pull-up when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in
High-Impedance state when JTAG scan is not enabled.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled
HIGH by an internal pull-up when not driven.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-
Reset state. This pin is pulled by an internal pull-up when not driven. This pin should
be pulsed LOW on power-up, or held LOW, to ensure that the device is in the normal
functional mode.
F32i
GND
ODE
Frame Pulse
I
B1
*See PBGA
Table Below
Output Drive Enable
I
A3
RX0-63
RX Input 0 to 63
I
*See PBGA
Table Below
A2
RESET
Device Reset:
I
R/W
S/A
Read/Write
Synchronous/
Asynchronous
Bus Mode
Test Clock
Test Serial Data In
Test Serial Data Out
Test Mode Select
Test Reset
I
I
E2
C1
TCK
TDI
TDO
TMS
TRST
I
I
O
I
I
D2
C3
D1
C2
D3
3
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL
TX0-7
TX16-23
TX32-39
TX48-55
NAME
TX Output
I/O
O
PBGA
PIN NO.
*See PBGA
Table Below
DESCRIPTION
Serial data Output Stream. These streams may have data rates of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s,16.384Mb/s, or 32.768Mb/s depending upon the selection in
Transmit Data Rate Selection Register (TDRSR). If G0/G2/G4/G6 are programmed to
32.768Mb/s mode the corresponding odd group is unavailable (G1/G3/G5G7).
When output streams are selected via TDRSR, these pins are the TX output streams.
When output enable indication function is selected, these pins reflect the active or High-
Impedance status for the corresponding TX output stream.
+3.3 Volt Power Supply.
TX8-15/OEI0-7
TX Output /Output
TX24-31/OEI16-23 Enable Indication
TX40-47/OEI32-39
TX56-63/OEI48-55
V
CC
O
*See PBGA
Table Below
*See PBGA
Table Below
PBGA PIN NUMBER TABLE
SYMBOL
A0-A15
D0-D15
GND
RX0-63
NAME
Address A0-15
Data Bus 0-15
Ground
RX Input 0 to 63
I
I/O
I
I/O
PIN NUMBER
E3, E4, F1, F2, F3, F4, G1, G2, G3, H1, H2, H3, J3, J2, J1, K3.
T2, T1, R1, P1, P2, N1, N2, N3, M1, M2, M3, M4, L1, L2, L3, K1.
G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10,K7, K8, K9, K10,
B3, A4, B4, C4, A5, B5, C5, D5, D11, C11, B11, A11, D12, C12, B12, A12, E13, D13, C13, B13, A13, D14, C14 , B14,
G16, G15, G14, H16, H15, H14, J14, J15, J16, K14, K15, K16, L13, L14, L15, L16, R14, T13, R13, P13, T12, R12, P12,
N12, T11, R11, P11, N11, T10, R10, P10, T9, N4, P4, R4, T4, P3, R3, T3, R2.
A6, B6, C6, D6, A7, B7, C7, A8
A14, B15, A15, A16, B16, C16, C15, D16
M13, M14, M15, M16, N13, N14, N15, N16
R9, P9, P8, R8. T8, P7, R7, T7
B8, C8, C9, B9, A9, C10, B10, A10.
D15, E16, E15, E14, F16, F15, F14, F13.
P14, P15, P16, R16, T16, T15, R15, T14.
N6, P6, R6, T6, N5, P5, R5, T5.
B2, D7, D8, D9, D10, G4, G13, H4, H13, J4, J13, K4, K13, N7, N8, N9, N10.
4
TX0-TX7
TX16-23
TX32-39
TX48-55
TX Output
O
TX8-15/OEI0-7
TX Output/Output
TX24-31/OEI16-23
TX40-47/OEI32-39
TX56-63/OEI48-55
Vcc
O
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
The IDT72V73263 is capable of switching up to 16,384 x 16,384 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per-channel basis.
The 64 serial input streams (RX) of the IDT72V73263 can be run at
2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s or 32.768Mb/s allowing 32,
64, 128, 256 or 512 channels per 125µs frame. The data rates on the output
streams can independently be programmed to run at any of these data rates.
With two main operating modes, Processor Mode and Connection Mode, the
IDT72V73263 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory.
As control and status information is critical in data transmission, the Processor
Mode is especially useful when there are multiple devices sharing the input and
output streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V73263
has a Frame Offset feature to allow individual streams to be offset from the frame
pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V73263 also provides a JTAG test access port, memory block
programming, Group Block Programming, RX/TX internal bypass, a simple
microprocessor interface and automatic ST-BUS
/GCI sensing to shorten
setup time, aid in debugging and ease use of the device without sacrificing
capabilities.
DESCRIPTION (CONTINUED):
MOD2-0 bits are set to 0-0-1 accordingly, that particular channel will be in
Constant Delay Mode. Finally, if the MOD2-0 bits are set to 0-0-0, that particular
channel will be in Variable Delay Mode.
SERIAL DATA INTERFACE TIMING
The master clock frequency of the IDT72V73263 is 32.768MHz, C32i. For
32.768Mb/s data rates, this results in a single-bit per clock. For 16.384Mb/s,
8.192Mb/s, 4.096Mb/s, and 2.048Mb/s this will result in two, four, eight, and
sixteen clocks per bit, respectively. The IDT72V73263 provides two different
interface timing modes, ST-BUS
or GCI. The IDT72V73263 automatically
detects the polarity of an input frame pulse and identifies it as either ST-BUS
or GCI.
For 32.768Mb/s, in ST-BUS
Mode, data is clocked out on a falling edge and
is clocked in on the subsequent rising-edge. For 16.384Mb/s, 8.192Mb/s,
4.096Mb/s, and 2.048Mb/s however there is not the typical associated clock
since the IDT72V73263 accepts only a 32.768MHz clock. As a result there will
be 2, 4, 8, and 16 clock between the 32.768Mb/s transmit edge and the
subsequently transmit edges. Although in this is the case, the IDT72V73263
will appropriately transmit and sample on the proper edge as if the respective
clock were present. See ST-BUS
Timing for detail.
For 32.768Mb/s, in GCI Mode, data is clocked out on a rising edge and is
clocked in on the subsequent falling-edge. For 16.384Mb/s, 8.192Mb/s,
4.096Mb/s, and 2.048Mb/s however, again there is not the typical associated
clock since the IDT72V73263 accepts only a 32.768MHz clock. As a result there
will 2, 4, 8, and 16 clocks between the 32.768Mb/s transmit edge and the other
transmit edges. Although this is the case, the IDT72V73263 will appropriately
transmit and sample on the proper edge as if the respective clock were present.
See GCI Bus Timing for detail.
DELAY THROUGH THE IDT72V73263
The switching of information from the input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabilities
on a per-channel basis. For voice applications, variable throughput delay is best
as it ensure minimum delay between input and output data. In wideband data
applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
The delay through the device varies according to the type of throughput delay
selected in the MOD bits of the Connection Memory.
VARIABLE DELAY MODE (MOD2-0 = 0-0-0)
In this mode, mostly for voice applications where minimum throughput delay
is desired, delay is dependent on the combination of source and destination
channels. The minimum delay achievable is a 3 channel periods of the slower
data rate.
CONSTANT DELAY MODE (MOD2-0 = 0-0-1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V73263, the minimum throughput delay achievable in Constant Delay
mode will be one frame plus one channel. See Table 14.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F32i) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the serial input streams
(Data Memory) or from the Connection Memory via the microprocessor or in
the case that RX input data is to be output, the addresses in Connection Memory
are used to specify a stream and channel of the input. The Connection Memory
is setup in such a way that each location corresponds to an output channel for
each particular stream. In that way, more than one channel can output the same
data. In Processor Mode, the microprocessor writes data to the Connection
Memory locations corresponding to the stream and channel that is to be output.
The lower half (8 least significant bits) of the Connection Memory LOW is output
every frame until the microprocessor changes the data or mode of the channels.
By using this Processor Mode capability, the microprocessor can access input
and output time-slots on a per-channel basis.
The three least significant bits of the Connection Memory HIGH are used to
control per-channel mode of the output streams. The MOD2-0 bits are used to
select Processor Mode, Constant or Variable Delay Mode, Bit Error Rate, and
the High-Impedance state of output drivers. If the MOD2-0 bits are set to 1-1-1
accordingly, only that particular output channel (8 bits) will be in the High-
Impedance state. If the MOD2-0 bits are set to 1-0-0 accordingly, that particular
channel will be in Processor Mode. If the MOD2-0 bits are set to 1-0-1 a Bit Error
Rate Test pattern will be transmitted for that time slot. See BERT section. If the
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