82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
Y
Supports the Pentium
TM
Processor at
iCOMP
TM
Index 510T60 MHz and iCOMP
Index 567T66 MHz
Supports the Pentium Processor at
iCOMP Index 735T90 MHz iCOMP Index
815T100 MHz and iCOMP Index 610T75
MHz
Supports Pipelined Addressing
Capability of the Pentium Processor
The 82430NX Drives 3 3V Signal Levels
on the CPU and Cache Interfaces
High Performance CPU PCI Memory
Interfaces via Posted Write and Read
Prefetch Buffers
Fully Synchronous PCI Interface with
Full Bus Master Capability
Supports the Pentium Processor
Internal Cache in Either Write-Through
or Write-Back Mode
Programmable Attribute Map of DOS
and BIOS Regions for System
Flexibility
Integrated Low Skew Clock Driver for
Distributing Host Clock
Integrated Second Level Cache
Controller
Integrated Cache Tag RAM
Write-Through and Write-Back Cache
Modes for the 82434LX
Write-Back for the 82434NX
82434NX Supports Low-Power Cache
Standby
Direct Mapped Organization
Supports Standard and Burst SRAMs
256-KByte and 512-KByte Sizes
Cache Hit Cycle of 3-1-1-1 on Reads
and Writes Using Burst SRAMs
Cache Hit Cycle of 3-2-2-2 on Reads
and 4-2-2-2 on Writes Using
Standard SRAMs
Y
Y
Y
Y
Y
Y
Integrated DRAM Controller
Supports 2 MBytes to 192 MBytes of
Cacheable Main Memory for the
82434LX
Supports 2 MBytes to 512 MBytes of
Cacheable Main Memory for the
82434NX
Supports DRAM Access Times of
70 ns and 60 ns
CPU Writes Posted to DRAM 4-1-1-1
Refresh Cycles Decoupled from ISA
Refresh to Reduce the DRAM
Access Latency
Six RAS Lines (82434LX)
Eight RAS Lines (82434NX)
Refresh by RAS -Only or CAS-
Before-RAS in Single or Burst
of Four
Host PCI Bridge
Translates CPU Cycles into PCI Bus
Cycles
Translates Back-to-Back Sequential
CPU Memory Writes into PCI Burst
Cycles
Burst Mode Writes to PCI in Zero PCI
Wait-States (i e Data Transfer Every
Cycle)
Full Concurrency Between CPU-to-
Main Memory and PCI-to-PCI
Transactions
Full Concurrency Between CPU-to-
Second Level Cache and PCI-to-Main
Memory Transactions
Same Cache and Memory System
Logic Design for ISA and EISA
Systems
Cache Snoop Filter Ensures Data
Consistency for PCI-to-Main Memory
Transactions
208-Pin QFP Package
Y
Y
Y
Y
Y
Y
Other brands and names are the property of their respective owners
December 1994
Order Number 290479-004
82434LX 82434NX
This document describes both the 82434LX and 82434NX Unshaded areas describe the 82434LX
Shaded areas like this one describe 82434NX operations that differ from the 82434LX
The 82434LX 82434NX PCI Cache Memory Controllers (PCMC) integrate the cache and main memory
DRAM control functions and provide bus control for transfers between the CPU cache main memory and the
PCI Local Bus The cache controller supports write-back (or write-through for 82434LX) cache policy and
cache sizes of 256-KBytes and 512-KBytes The cache memory can be implemented with either standard or
burst SRAMs The PCMC cache controller integrates a high-performance Tag RAM to reduce system cost
2
82434LX 82434NX
290479 –1
NOTE
RAS 7 6
and MA11 are only on the 82434NX CCS 1 0 functionality is only on the 82434NX
Simplified Block Diagram of the PCMC
3
82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
CONTENTS
1 0 ARCHITECTURAL OVERVIEW
1 1 System Overview
1 1 1 BUS HIERARCHY CONCURRENT OPERATIONS
1 1 2 BUS BRIDGES
1 2 PCMC Overview
1 2 1 CACHE OPERATIONS
1 2 1 1 Cache Consistency
1 2 2 ADDRESS DATA PATHS
1 2 2 1 Read Write Buffers
1 2 3 HOST PCI BRIDGE OPERATIONS
1 2 4 DRAM MEMORY OPERATIONS
1 2 5 3 3V SIGNALS
2 0 SIGNAL DESCRIPTIONS
2 1 Host Interface
2 2 DRAM Interface
2 3 Cache Interface
2 4 PCI Interface
2 5 LBX Interface
2 6 Reset And Clock
3 0 REGISTER DESCRIPTION
3 1 I O Mapped Registers
3 1 1 CONFADD CONFIGURATION ADDRESS REGISTER
3 1 2 CSE CONFIGURATION SPACE ENABLE REGISTER
3 1 3 TRC TURBO-RESET CONTROL REGISTER
3 1 4 FORW FORWARD REGISTER
3 1 5 PMC PCI MECHANISM CONTROL REGISTER
3 1 6 CONFDATA CONFIGURATION DATA REGISTER
3 2 PCI Configuration Space Mapped Registers
3 2 1 CONFIGURATION SPACE ACCESS MECHANISM
3 2 1 1 Access Mechanism 1
3 2 1 2 Access Mechanism 2
3 2 2 VID VENDOR IDENTIFICATION REGISTER
3 2 3 DID DEVICE IDENTIFICATION REGISTER
PAGE
10
10
10
13
13
14
15
15
15
15
16
16
16
17
22
23
24
28
28
30
31
31
32
33
34
34
34
35
36
36
37
40
40
4
CONTENTS
3 2 4 PCICMD PCI COMMAND REGISTER
3 2 5 PCISTS PCI STATUS REGISTER
3 2 6 RID REVISION IDENTIFICATION REGISTER
3 2 7 RLPI REGISTER-LEVEL PROGRAMMING INTERFACE REGISTER
3 2 8 SUBC SUB-CLASS CODE REGISTER
3 2 9 BASEC BASE CLASS CODE REGISTER
3 2 10 MLT MASTER LATENCY TIMER REGISTER
3 2 11 BIST BIST REGISTER
3 2 12 HCS HOST CPU SELECTION REGISTER
3 2 13 DFC DETURBO FREQUENCY CONTROL REGISTER
3 2 14 SCC SECONDARY CACHE CONTROL REGISTER
3 2 15 HBC HOST READ WRITE BUFFER CONTROL
3 2 16 PBC PCI READ WRITE BUFFER CONTROL REGISTER
3 2 17 DRAMC DRAM CONTROL REGISTER
3 2 18 DRAMT DRAM TIMING REGISTER
3 2 19 PAM PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM 6 0 )
3 2 20 DRB DRAM ROW BOUNDARY REGISTERS
3 2 20 1 82434LX Description
3 2 20 2 82434NX Description
3 2 21 DRBE DRAM ROW BOUNDARY EXTENSION REGISTER
3 2 22 ERRCMD ERROR COMMAND REGISTER
3 2 23 ERRSTS ERROR STATUS REGISTER
3 2 24 SMRS SMRAM SPACE REGISTER
3 2 25 MSG MEMORY SPACE GAP REGISTER
3 2 26 FBR FRAME BUFFER RANGE REGISTER
4 0 PCMC ADDRESS MAP
4 1 CPU Memory Address Map
4 2 System Management RAM SMRAM
4 3 PC Compatibility Range
4 4 I O Address Map
PAGE
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ARM技术
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