82091AA
ADVANCED INTEGRATED PERIPHERAL (AIP)
Y
Single-Chip PC Compatible I O Solution
for Notebook and Desktop Platforms
82078 Floppy Disk Controller Core
Two 16550 Compatible UARTs
One Multi-Function Parallel Port
IDE Interface
Integrated Back Power Protection
Integrated Game Port Chip Select
5V or 3 3V Supply Operation with 5V
Tolerant Drive Interface
Full Power Management Support
Supports Type F DMA Transfers for
Faster I O Performance
No Wait-State Host I O Interface
Programmable Interrupt Interfaces
Single Crystal Oscillator Clock
(24 MHz)
Software Detectable Device ID
Comprehensive Powerup
Configuration
The 82091AA is 100 Percent
Compatible with EISA ISA and AT
Host Interface Features
8-Bit Zero Wait-State ISA Bus
Interface
DMA with Type F Transfers
Five Programmable ISA Interrupt
Lines
Internal Address Decoder
Parallel Port Features
All IEEE Standard 1284 Protocols
Supported (Compatibility Nibble
Byte EPP and ECP)
Peak Bi-Directional Transfer Rate of
2 MB sec
Provides Interface for Low-Cost
Engineless Laser Printer
16-Byte FIFO for ECP
Interface Backpower Protection
Y
Floppy Disk Controller Features
100 Percent Software Compatible
with Industry Standard 82077SL and
82078
Integrated Analog Data Separator
250K 300K 500K and 1 MBits sec
Programmable Powerdown
Command
Auto Powerdown and Wakeup
Modes
Integrated Tape Drive Support
Perpendicular Recording Support for
4 MB Drives
Programmable Write Pre-
Compensation Delays
256 Track Direct Address Unlimited
Track Support
16-Byte FIFO
Supports 2 or 4 Drives
16550 Compatible UART Features
Two Independent Serial Ports
Software Compatible with 8250 and
16450 UARTs
16-Byte FIFO per Serial Port
Two UART Clock Sources Supports
MIDI Baud Rate
IDE Interface Features
Generates Chip Selects for IDE
Drives
Integrated Buffer Control Logic
Dual IDE Interface Support
Power Management Features
Transparent to Operating Systems
and Applications Programs
Independent Power Control for Each
Integrated Device
100-Pin QFP Package
(See Packaging Spec 240800)
Y
Y
Y
Y
Y
Y
Y
The 82091AA Advanced Integrated Peripheral (AIP) is an integrated I O solution containing a floppy disk
controller 2 serial ports a multi-function parallel port an IDE interface and a game port on a single chip The
integration of these I O devices results in a minimization of form factor cost and power consumption The
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1996
December 1995
Order Number 290486-003
82091AA
floppy disk controller is the 82078 core The serial ports are 16550 compatible The parallel port supports all of
the IEEE Standard 1284 protocols (ECP EPP Byte Compatibility and Nibble) The IDE interface supports
8- or 16-bit programmed I O and 16-bit DMA The Host Interface is an 8-bit ISA interface optimized for type
‘‘F’’ DMA and no wait-state I O accesses Improved throughput and performance the 82091AA contains six
16-byte FIFOs – two for each serial port one for the parallel port and one for the floppy disk controller The
82091AA also includes power management and 3 3V capability for power sensitive applications such as
notebooks The 82091AA supports both motherboard and add-in card configurations
290486 –1
Figure 1 82091AA Advanced Integrated Peripheral Block Diagram
2
82091AA
ADVANCED INTEGRATED PERIPHERAL (AIP)
CONTENTS
1 0 OVERVIEW
1 1 3 3 5V Operating Modes
2 0 SIGNAL DESCRIPTION
2 1 Host Interface Signals
2 2 Floppy Disk Controller Interface
2 3 Serial Port Interface
2 4 IDE Interface
2 5 Parallel Port External Buffer Control Game Port
2 6 Parallel Port Interface
2 6 1 COMPATIBILITY PROTOCOL SIGNAL DESCRIPTION
2 6 2 NIBBLE PROTOCOL SIGNAL DESCRIPTION
2 6 3 BYTE MODE SIGNAL DESCRIPTION
2 6 4 ENHANCED PARALLEL PORT (EPP) PROTOCOL SIGNAL DESCRIPTION
2 6 5 EXTENDED CAPABILITIES PORT (ECP) PROTOCOL SIGNAL DESCRIPTION
2 7 Hard Reset Signal Conditions
2 8 Power And Ground
3 0 I O ADDRESS ASSIGNMENTS
4 0 AIP CONFIGURATION
4 1 Configuration Registers
4 1 1 CFGINDX CFGTRGT CONFIGURATION INDEX REGISTER AND TARGET
PORT
4 1 2 AIPID AIP IDENTIFICATION REGISTER
4 1 3 AIPREV AIP REVISION IDENTIFICATION
4 1 4 AIPCFG1 AIP CONFIGURATION 1 REGISTER
4 1 5 AIPCFG2 AIP CONFIGURATION 2 REGISTER
4 1 6 FCFG1 FDC CONFIGURATION REGISTER
4 1 7 FCFG2 FDC POWER MANAGEMENT AND STATUS REGISTER
4 1 8 PCFG1 PARALLEL PORT CONFIGURATION REGISTER
4 1 9 PCFG2 PARALLEL PORT POWER MANAGEMENT AND STATUS
REGISTER
4 1 10 SACFG1 SERIAL PORT A CONFIGURATION REGISTER
4 1 11 SACFG2 SERIAL PORT A POWER MANAGEMENT AND STATUS
REGISTER
4 1 12 SBCFG1 SERIAL PORT B CONFIGURATION REGISTER
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3
CONTENTS
4 1 13 SBCFG2 SERIAL PORT B POWER MANAGEMENT AND STATUS
REGISTER
4 1 13 1 Serial Port A B Configuration Registers SxEN and SxDPDN Bits
4 1 14 IDECFG IDE CONFIGURATION REGISTER
4 2 Hardware Configuration
4 2 1 SELECTING THE HARDWARE CONFIGURATION MODE
4 2 2 SELECTING HARDWARE CONFIGURATION MODE OPTIONS
4 2 3 HARDWARE CONFIGURATION TIMING RELATIONSHIPS
4 2 4 HARDWARE BASIC CONFIGURATION
4 2 5 HARDWARE EXTENDED CONFIGURATION MODE
4 2 6 SOFTWARE ADD-IN CONFIGURATION
4 2 7 SOFTWARE MOTHERBOARD CONFIGURATION
5 0 HOST INTERFACE
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6 0 PARALLEL PORT
6 1 Parallel Port Registers
6 1 1 ISA-COMPATIBLE AND PS 2-COMPATIBLE MODES
6 1 1 1 PDATA Parallel Port Data Register (ISA-Compatible and PS 2-Compatible
Modes)
6 1 1 2 PSTAT Status Register (ISA-Compatible and PS 2-Compatible Modes)
6 1 1 3 PCON Control Register (ISA-Compatible and PS 2-Compatible Mode)
6 1 2 EPP MODE
6 1 2 1 PDATA Parallel Port Data Register (EPP Mode)
6 1 2 2 PSTAT Status Register (EPP Mode)
6 1 2 3 PCON Control Register (EPP Mode)
6 1 2 4 ADDSTR EPP Auto Address Strobe Register (EPP Mode)
6 1 2 5 DATASTR Auto Data Strobe Register (EPP Mode)
6 1 3 ECP MODE
6 1 3 1 ECPAFIFO ECP Address RLE FIFO Register (ECP Mode)
6 1 3 2 PSTAT Status Register (ECP Mode)
6 1 3 3 PCON Control Register (ECP Mode)
6 1 3 4 SDFIFO Standard Parallel Port Data FIFO
6 1 3 5 DFIFO Data FIFO (ECP Mode)
6 1 3 6 TFIFO ECP Test FIFO Register (ECP Mode)
6 1 3 7 ECPCFGA ECP Configuration A Register (ECP Mode)
6 1 3 8 ECPCFGB ECP Configuration B Register (ECP Mode)
6 1 3 9 ECR ECP Extended Control Register (ECP Mode)
6 2 Parallel Port Operations
6 2 1 ISA-COMPATIBLE AND PS 2-COMPATIBLE MODES
6 2 2 EPP MODE
6 2 3 ECP MODE
4
CONTENTS
6 2 3 1 FIFO Operations
6 2 3 2 DMA Transfers
6 2 3 3 Reset FIFO and DMA Terminal Count Interrupt
6 2 3 4 Programmed I O Transfers
6 2 3 5 Data Compression
6 2 4 PARALLEL PORT EXTERNAL BUFFER CONTROL
6 2 5 PARALLEL PORT SUMMARY
7 0 SERIAL PORT
7 1 Register Description
7 1 1 THR(A B) TRANSMITTER HOLDING REGISTER
7 1 2 RBR(A B) RECEIVER BUFFER REGISTER
7 1 3 DLL(A B) DLM(A B) DIVISOR LATCHES (LSB AND MSB) REGISTERS
7 1 4 IER(A B) INTERRUPT ENABLE REGISTER
7 1 5 IIR(A B) INTERRUPT IDENTIFICATION REGISTER
7 1 6 FCR(A B) FIFO CONTROL REGISTER
7 1 7 LCR(A B) LINE CONTROL REGISTER
7 1 8 MCR(A B) MODEM CONTROL REGISTER
7 1 9 LSR(A B) LINE STATUS REGISTER
7 1 10 MSR(A B) MODEM STATUS REGISTER
7 1 11 SCR(A B) SCRATCHPAD REGISTER
7 2 FIFO Operations
7 2 1 FIFO INTERRUPT MODE OPERATION
7 2 2 FIFO POLLED MODE OPERATION
8 0 FLOPPY DISK CONTROLLER
8 1 Floppy Disk Controller Registers
8 1 1 SRB STATUS REGISTER B (EREG EN
e
1)
8 1 2 DOR DIGITAL OUTPUT REGISTER
8 1 3 TDR ENHANCED TAPE DRIVE REGISTER
8 1 4 MSR MAIN STATUS REGISTER
8 1 5 DSR DATA RATE SELECT REGISTER
8 1 6 FDCFIFO FDC FIFO (DATA)
8 1 7 DIR DIGITAL INPUT REGISTER
8 1 8 CCR CONFIGURATION CONTROL REGISTER
8 2 Reset
8 2 1 HARD RESET AND CONFIGURATION REGISTER RESET
8 2 2 DOR RESET vs DSR RESET
8 3 DMA Transfers
8 4 Controller Phases
8 4 1 COMMAND PHASE
8 4 2 EXECUTION PHASE
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