HS-81C55RH,
HS-81C56RH
March 1996
Radiation Hardened
256 x 8 CMOS RAM
Description
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
Features
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 10
5
RAD(Si)
- Transient Upset > 1 x 10
8
RAD(Si)/s
- Latch-Up Free > 1 x 10
12
RAD(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current 200µA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55
o
C to +125
o
C
Functional Diagram
IO/M
AD0 - AD7
CE OR CE†
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
†81C55RH
= CE
81C56RH = CE
TIMER
C
PORT C
8
PC0 - PC5
VDD (10V)
GND
256 x 8
STATIC
RAM
A
PORT A
8
PA0 - PA7
PORT B
B
8
PB0 - PB7
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
5962R9XXXX01QXC
5962R9XXXX01VXC
5962R9XXXX02QRC
5962R9XXXX02VRC
5962R9XXXX02QXC
5962R9XXXX02VXC
HS1-81C55RH/Sample
HS9-81C55RH/Sample
HS1-81C56RH/Sample
HS9-81C56RH/Sample
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
Sample
Sample
Sample
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518056
3039.1
HS-81C55RH, HS-81C56RH
Pinouts
40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
PC3
PC4
TIMER IN
RESET
PC5
TIMER OUT
IO / M
CE or CE*
1
2
3
4
5
6
7
8
40 VDD
39 PC2
38 PC1
37 PC0
36 PB7
35 PB6
34 PB5
33 PB4
32 PB3
31 PB2
30 PB1
29 PB0
28 PA7
27 PA6
26 PA5
25 PA4
24 PA3
23 PA2
22 PA1
21 PA0
RD 9
WR 10
*81C55RH = CE
81C56RH = CE
ALE 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INTERSIL OUTLINE K42.A
TOP VIEW
PC3
PC4
TIMER IN
RESET
PC5
TIMER OUT
IO/M
CE OR CE
RD
WR
ALE
AD0
AD1
AD2
AD3
NC
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
NC
PA4
PA3
PA2
PA1
PA0
Spec Number
2
518056
HS-81C55RH, HS-81C56RH
Pin Description
SYMBOL
RESET
TYPE
I
NAME AND FUNCTION
Reset:
Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET
OUT). Input high on this line resets the chip and initializes the three I/O ports to input mode. The width
of RESET pulse should typically be two HS-80C85RH clock cycle times.
Address/Data:
Tri-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus.
The 8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling
edge of ALE. The address can be either for the memory section or the I/O section depending on the IO/
M input. The 8-bit data is either written into the chip or read from the chip, depending on the WR or RD
input signal.
Chip Enable:
On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin
is CE and is ACTIVE HIGH.
Read Control:
Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/
M pin is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O
port or command/status registers will be read to the AD bus.
Write Control:
Input low on this line with the Chip Enable active causes the data on the Address/Data
bus to be written to the RAM or I/O ports and command/status register, depending on IO/M.
Address Latch Enable:
This control signal latches both the address on the AD0 - AD7 lines and the
state of the Chip Enable and IO/M into the chip at the falling edge of ALE.
I/O Memory:
Selects memory if low and I/O and command/status registers if high.
Port A:
These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port B:
These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port C:
These 6 pins can function as either input port, output port, or as control signals for PA and PB.
Programming is done through the command register. When PC0 - PC5 are used as control signals, they
will provide the following:
PC0 - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PC5 - B STB (Port B Strobe)
Timer Input:
Input to the counter-timer.
Timer Output:
This output can be either a square wave or a pulse, depending on the timer mode.
Voltage:
+5V.
Ground:
Ground reference.
AD0 - AD7
I/O
CE or CE
RD
I
I
WR
ALE
IO/M
PA0 - PA7 (8)
PB0 - PB7 (8)
PC0 - PC7 (8)
I
I
I
I/O
I/O
I/O
TIMER IN
TIMER OUT
VDD
GND
I
O
I
I
Spec Number
3
518056
Specifications HS-81C55RH, HS-81C56RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
Typical Derating Factor . . . . . . . . . . . . 2mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance
θ
JA
θ
JC
o
C/W 5.0
o
C/W
SBDIP Package . . . . . . . . . . . . . . . . . . . . 40.0
Ceramic Flatpack Package . . . . . . . . . . . 45.0
o
C/W 5.0
o
C/W
Maximum Package Power Dissipation at +125
o
C
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.0mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 22.2mW/
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
7, 8A, 8B
LIMITS
TEMPERATURE
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
MIN
-
-1
-
4.25
-
-
-
MAX
1
-
0.5
-
200
2
-
UNITS
µA
µA
V
V
µA
mA
-
PARAMETERS
High Input Leakage
Current
Low Input Leakage
Current
Low Output Voltage
High Output Voltage
Static Current
Dynamic Current
Functional Tests
SYMBOL
IIH
IIL
VOL
VOH
IDDSB
IDDOP
FT
CONDITIONS
VDD = 5.25V, VIN = 0V,
Pin under test = VDD
VDD = 5.25V, VIN = 5.25V,
Pin under test = 0V
VDD = 5.25V, IOL = 2mA
VDD = 4.75V, IOH = 2mA
VDD = 5.25V
VDD = 5.25V, f = 1MHz
VDD = 4.75V and 5.25V,
VIH = VDD-0.5V, VIL = 0.8V
NOTE: All devices are guaranteed at worst case limits and over radiation. Dynamic current is proportional to operating frequency (2mA/MHz).
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
LIMITS
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
MIN
60
60
200
-
-
200
20
250
200
25
MAX
-
-
-
250
500
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETERS
Address Latch Setup Time
Address Hold Time After Latch
Latch to READ/WRITE Control
Valid Data Out From Read Control
Address Stable to Data Out Valid
Latch Enable Width
READ/WRITE Control to Latch
Enable
READ/WRITE Control Width
Data In to WRITE Setup Time
Data In Hold Time After WRITE
SYMBOL
TAL
TLA
TLC
TRD
TAD
TLL
TCL
TCC
TDW
TWD
CONDITIONS
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4,7
Notes 1, 4
Notes 1, 4
Notes 1, 4
Spec Number
4
518056
Specifications HS-81C55RH, HS-81C56RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
LIMITS
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
100
100
-
-
-
-
-
120
40
115
MIN
-
50
15
-
150
-
-
MAX
300
-
-
300
-
300
300
360
-
-
300
300
340
300
300
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETERS
WRITE to Port Output
Port Input Setup Time
Port Input Hold Time
Strobe to Buffer Full
Strobe Width
READ to Buffer Empty
Strobe to INTR Off
READ to INTR Off
Port Setup Time to Strobe
Post Hold Time After Strobe
Strobe to Buffer Empty
WRITE to Buffer full
WRITE to INTR Off
TIMER-IN to TIMER OUT Low
TIMER-IN to TIMER-OUT High
Data Bus Enable from READ Control
TIMER-IN Low Time
TIMER-IN High Time
NOTES:
SYMBOL
TWP
TPR
TRP
TSBF
TSS
TRBE
TSI
TRDI
TPSS
TPHS
TSBE
TWBF
TWI
TTL
TTH
TRDE
T1
T2
CONDITIONS
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4, 5
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4, 6
Notes 1, 4
1. All devices guaranteed at worst case limits and over radiation.
2. Operating supply current (IDDOP) is proportional to operating frequency.
3. Output timings are measured with purely capacitive load.
4. For design purposes the limits are given as shown. For compatibility with the 80C85RH microprocessor, the AC parameters are tested
as maximums.
5. Parameter tested as part of the functional test. No read and record data available.
6. At low temperature, T1 is measured down to 10ns. If the reading is less than 10ns, the parameter will read 10ns.
7. Read and Record data available on failing data only.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERS
Input Capacitance
I/O Capacitance
Output Capacitance
Data Bus Float After
READ
Recovery Time Between
Controls
SYMBOL
CIN
CI/O
COUT
TRDF
TRV
CONDITIONS
VDD = Open, f = 1MHz, All measurements
referenced to device ground
VDD = Open, f = 1MHz, All measurements
referenced to device ground
VDD = Open, f = 1MHz, All measurements
referenced to device ground
VDD = 4.75V
VDD = 4.75V
TEMPERATURE
T
A
= +25
o
C
T
A
= +25
o
C
T
A
= +25
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
MIN
-
-
-
10
-
MAX
10
12
10
100
220
UNITS
pF
pF
pF
ns
ns
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
Spec Number
5
518056
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