SPANSION Flash Memory
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20872-3E
PAGE MODE FLASH MEMORY
CMOS
16M (2M
×
8/1M
×
16) BIT
MBM29PL160TD/BD
-75/90
s
DESCRIPTION
The MBM29PL160TD/BD is a 16 M-bit, 3.0 V-only Flash memory organized as 2 M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (1), and 44-pin SOP packages. The
device is designed to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V
V
CC
are not required for write or erase operations. The device can also be reprogrammed in standard EPROM
programmers.
(Continued)
s
PRODUCT LINE UP
Part No.
Ordering Part No.
V
CC
= 3.0 V
+0.6 V
–0.3 V
MBM29PL160TD/160BD
-75
75
25
75
25
-90
90
35
90
35
Max Address Access Time (ns)
Max Page Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
s
PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
44-pin plastic SOP
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(FPT-44P-M16)
MBM29PL160TD/BD
-75/90
(Continued)
The standard MBM29PL160TD/BD offers access times of 75 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29PL160TD/BD is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29PL160TD/BD is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 4.8 second (If already preprogrammed).
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29PL160TD/BD is erased when shipped from the
factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
or by the Toggle Bit feature on DQ
6
output pin. Once the end of a program or erase cycle has been comleted,
the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29PL160TD/BD memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29PL160TD/BD
-75/90
s
FEATURES
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with MASK ROM pinouts
48-pin TSOP (1) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 program/erase cycles
• High performance
25 ns maximum page access time (75 ns maximum random access time)
• An 8 words page read mode function
• Sector erase architecture
One 8 K word, two 4 K words, one 112 K word, and seven 128 K words sectors in word mode
One 16 K byte, two 8 K bytes, one 224 K byte, and seven 256 K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded program
TM
* Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Temporary sector unprotection
Temporary sector unprotection with the software command
• 5 V tolerant (Data, Address, and Control Signals)
• In accordance with CFI (Common Flash Memory Interface)
*:
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MBM29PL160TD/BD
-75/90
s
PIN ASSIGNMENTS
SOP
(Marking Side)
WE
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
N.C.
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
CE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
N.C.
WE
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
N.C.
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
SS
V
CC
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
N.C.
BYTE
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
WE
N.C.
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSOP(1)
(Marking Side)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C.
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
V
CC
V
SS
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
N.C.
Normal Bend
(FPT-48P-M19)
(Marking Side)
Reverse Bend
(FPT-44P-M16)
(FPT-48P-M20)
4
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