SPECIAL ENVIRONMENT 80960CA-25 -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Two Instructions Clock Sustained Execution
Four 59 Mbytes s DMA Channels with Data Chaining
Demultiplexed 32-bit Burst Bus with Pipelining
Y
32-bit Parallel Architecture
Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulates 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model
Fast Procedure Call Return Model
Full Procedure Call in 4 Clocks
On-Chip Register Cache
Caches Registers on Call Ret
Minimum of 6 Frames Provided
Up to 15 Programmable Frames
On-Chip instruction Cache
1 Kbyte Two-Way Set Associative
128-bit Path to instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
High Bandwidth On-Chip Data RAM
1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access
Y
Four On-Chip DMA Channels
59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method
32-Bit Demultiplexed Burst Bus
128-bit internal Data Paths to
and
from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8- 16- or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
Selectable Big or Little Endian Byte
Ordering
High-Speed Interrupt Controller
Up to 248 External interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four internal DMA Interrupts
Separate Non-maskable interrupt Pin
Context Switch in 750 ns Typical
Product Grades Available
SE3
b
40 C to
a
110 C
Y
Y
Y
Y
Y
Y
Y
Y
December 1994
Order Number 271327-001
SPECIAL ENVIRONMENT 80960CA-25 -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
CONTENTS
1 0 PURPOSE
2 0 80960CA OVERVIEW
2 1 The C-Series Core
2 2 Pipelined Burst Bus
2 3 Flexible DMA Controller
2 4 Priority Interrupt Controller
2 5 Instruction Set Summary
3 0 PACKAGE INFORMATION
3 1 Package Introduction
3 2 Pin Descriptions
3 3 80960CA Mechanical Data
3 3 1 80960CA PGA Pinout
3 4 Package Thermal Specifications
3 5 Stepping Register Information
3 6 Suggested Sources for 80960CA Accessories
4 0 ELECTRICAL SPECIFICATIONS
4 1 Absolute Maximum Ratings
4 2 Operating Conditions
4 3 Recommended Connections
4 4 DC Specifications
4 5 AC Specifications
4 5 1 AC Test Conditions
4 5 2 AC Timing Waveforms
4 5 3 Derating Curves
5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE
6 0 BUS WAVEFORMS
7 0 REVISION HISTORY
PAGE
5
5
6
6
6
6
7
8
8
8
15
15
19
21
21
22
22
22
22
23
24
28
28
32
34
35
62
2
CONTENTS
LIST OF FIGURES
Figure 1 80960CA Block Diagram
Figure 2 80960CA PGA Pinout View from Top (Pins Facing Down)
Figure 3 80960CA PGA Pinout View from Bottom (Pins Facing Up)
Figure 4 Measuring 80960CA PGA Case Temperature
Figure 5 Register g0
Figure 6 AC Test Load
Figure 7 Input and Output Clocks Waveform
Figure 8 CLKIN Waveform
Figure 9 Output Delay and Float Waveform
Figure 10 Input Setup and Hold Waveform
Figure 11 NMI XINT7 0 Input Setup and Hold Waveform
Figure 12 Hold Acknowledge Timings
Figure 13 Bus Backoff (BOFF) Timings
Figure 14 Relative Timings Waveforms
Figure 15 Output Delay or Hold vs Load Capacitance
Figure 16 Rise and Fall Time Derating at Highest Operating Temperature
and Minimum V
CC
Figure 17 I
CC
vs Frequency and Temperature
Figure 18 Cold Reset Waveform
Figure 19 Warm Reset Waveform
Figure 20 Entering the ONCE State
Figure 21 Clock Synchronization in the 2-x Clock Mode
Figure 22 Clock Synchronization in the 1-x Clock Mode
Figure 23 Non-Burst Non-Pipelined Requests without Wait States
Figure 24 Non-Burst Non-Pipelined Read Request with Wait States
Figure 25 Non-Burst Non-Pipelined Write Request with Wait States
Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus
Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus
Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus
Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus
Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus
Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus
Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus
Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus
Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus
Figure 35 Burst Pipelined Read Request with Wait States 32-Bit Bus
Figure 36 Burst Pipelined Read Request with Wait States 16-Bit Bus
Figure 37 Burst Pipelined Read Request with Wait States 8-Bit Bus
PAGE
5
17
18
19
21
28
28
28
29
29
30
30
31
32
32
33
33
35
36
37
38
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
3
CONTENTS
LIST OF FIGURES
(Continued)
Figure 38 Using External READY
Figure 39 Terminating a Burst with BTERM
Figure 40 BOFF Functional Timing
Figure 41 HOLD Functional Timing
Figure 42 DREQ and DACK Functional Timing
Figure 43 EOP Functional Timing
Figure 44 Terminal Count Functional Timing
Figure 45 FAIL Functional Timing
Figure 46 A Summary of Aligned and Unaligned Transfers for Little Endian Regions
Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions
(Continued)
Figure 48 Idle Bus Operation
LIST OF TABLES
Table 1 80960CA Instruction Set
Table 2 Pin Description Nomenclature
Table 3 80960CA Pin Description External Bus Signals
Table 4 80960CA Pin Description Processor Control Signals
Table 5 80960CA Pin Description DMA and Interrupt Unit Control Signals
Table 6 80960CA PGA Pinout In Signal Order
Table 7 80960CA PGA Pinout In Pin Order
Table 8 Maximum T
A
at Various Airflows in C
Table 9 80960CA PGA Package Thermal Characteristics
Table 10 Die Stepping Cross Reference
Table 11 Operating Conditions (80960CA-25 -16)
Table 12 DC Characteristics
Table 13 80960CA AC Characteristics (25 MHz)
Table 14 80960CA AC Characteristics (16 MHz)
Table 15 Reset Conditions
Table 16 Hold Acknowledge and Backoff Conditions
PAGE
54
55
56
57
58
58
59
59
60
61
62
7
8
9
12
14
15
16
19
20
21
22
23
24
26
34
34
4
SPECIAL ENVIRONMENT 80960CA-25 -16
A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system’s high-
speed external memory sub-system In addition the
80960CA’s on-chip caching of instructions proce-
dure context and critical program data substantially
decouple system performance from the wait states
associated with accesses to the system’s slower
cost sensitive main memory subsystem
The 80960CA bus controller integrates full wait state
and bus width control for highest system perform-
ance with minimal system design complexity Un-
aligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip DMA channels perform single-
cycle or two-cycle transfers data packing and un-
packing and data chaining Block transfers in addi-
tion to source or destination synchronized trans-
fers are provided
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns
1 0 PURPOSE
This document provides electrical characteristics for
the 25 and 16 MHz versions of the 80960CA For a
detailed description of any 80960CA functional
topic other than parametric performance consult
the
80960CA Product Overview
(Order No 270669)
or the
i960 CA Microprocessor User’s Manual
(Or-
der No 270710) To obtain data sheet updates and
errata please call Intel’s FaxBACK data-on-de-
mand system (1-800-628-2283 or 916-356-3105)
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600)
2 0 80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift
64-bit operands and configure on-chip hardware
Multiple 128-bit internal buses on-chip instruction
caching and a sophisticated instruction scheduler al-
low the processor to sustain execution of two in-
structions every clock and peak at execution of
three instructions per clock
271327 –1
Figure 1 80960CA Block Diagram
5
为我们提建议&公告
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
