Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
FEATURES
•
16-bit transparent latch
•
Multiple V
CC
and GND pins minimize
switching noise
DESCRIPTION
The MB2373 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The MB2373 device is a dual octal
transparent latch coupled to two sets of eight
3-State output buffers. The two sections of
the device are controlled independently by
Enable (nE) and Output Enable (nOE) control
gates.
The data on each set of D inputs are
transferred to the latch outputs when the
Latch Enable (nE) input is High. The latch
remains transparent to the data inputs while
nE is High, and stores the data that is present
one setup time before the High-to-Low
enable transition.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. Each
active-Low Output Enable (nOE) controls
eight 3-State buffers independent of the latch
operation.
When nOE is Low, the latched or transparent
data appears at the outputs. When nOE is
High, the outputs are in the High–impedance
“OFF” state, which means they will neither
drive nor load the bus.
•
Power-up 3-State
•
Live insertion/extraction permitted
•
Power-up reset
•
3-State output buffers
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per
JEDEC JC40.2 Std 17
•
ESD protection exceeds 2000V per MIL
STD 883 Method 3015 and 200V per
Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5V
TYPICAL
2.9
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
52–pin plastic Quad Flat Pack
TEMPERATURE RANGE
–40°C to +85°C
ORDER CODE
MB2373BB
DRAWING NUMBER
1418B
PIN CONFIGURATION
GND
GND
GND
1OE
1Q3
1Q2
1Q1
1Q0
1D0
1D1
1D2
1D3
1E
LOGIC SYMBOL
52 51
V
CC
1Q4
1Q5
GND
1
2
3
4
5
6
7
8
9
50 49 48 47
46 45 44 43 42
41 40
39 V
CC
38 1D4
37 1D5
36 GND
35 1D6
48
49
51
52
2
1Q0 1OE
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1E
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
44
43
41
40
38
37
35
34
8
9
11
12
14
15
17
18
2Q0 2OE
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2E
2D0
2D21
2D2
2D3
2D4
2D5
2D6
2D7
32
31
29
28
26
25
23
22
47 45
19 21
1Q6
1Q7
GND
MB2373
52–pin PQFP
34 1D7
33 GND
32 2D0
31 2D1
30 GND
29 2D2
28 2D3
27 V
CC
2Q0
2Q1
GND 10
2Q2 11
2Q3 12
V
CC
13
14 15 16
2Q4
2Q5
GND
17 18 19 20
2Q6
2Q7
2OE
GND
21 22 23 24 25
2E
GND
2D6
2D5
2D7
26
2D4
August 23, 1993
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5
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853-1669 10587
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
PIN DESCRIPTION
PIN NUMBER
44, 43, 41, 40,38, 37, 35, 34,
32, 31, 29, 28, 26, 25, 23, 22
48, 49, 51, 52, 2, 3, 5, 6,
8, 9, 11, 12, 14, 15, 17, 18
47, 19
45, 21
4, 7, 10, 16, 20, 24, 30,
33, 36, 42, 46, 50
1, 13, 27, 39
SYMBOL
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
1E, 2E
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active–Low)
Enable inputs (active–High)
Ground (0V)
Positive supply voltage
FUNCTION
LOGIC SYMBOL (IEEE/IEC)
47
45
C1
EN
19
21
C1
EN
44
43
41
40
38
37
35
34
1D
48
49
51
52
2
3
5
6
32
31
29
28
26
25
23
22
1D
8
9
11
12
14
15
17
18
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
August 23, 1993
2
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
L
nE
H
H
↓
↓
L
nDx
L
H
i
h
X
INTERNAL
REGISTER
L
H
L
H
NC
OUTPUTS
nQ0 – nQ7
L
H
L
H
NC
Enable and read register
Latch and read register
Hold
Disable outputs
OPERATING MODE
H =
h =
L =
l =
NC=
X =
Z =
↓
=
H
L
X
NC
Z
H
H
Dn
Dn
Z
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off” state
High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
August 23, 1993
3
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
–32
64
10
+85
LIMITS
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
MIN
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST
I
I
I
OFF
I
PU/PD
I
OZH
I
OZL
I
O
I
CEX
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Low-level output voltage
Power-up output voltage
3
Input leakage current
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output current
1
Output High leakage current
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= GND
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–50
2.5
3.0
2.0
TYP
–0.9
2.9
3.4
2.4
0.42
0.13
±0.01
±5.0
±5.0
5.0
–5.0
–70
5.0
120
44
120
0.5
0.55
0.55
±1.0
±100
±50
50
–50
–180
50
250
60
250
1.5
–50
MAX
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
±50
50
–50
–180
50
250
60
250
1.5
T
amb
= –40°C
to +85°C
MIN
MAX
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
µA
µA
mA
µA
mA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10% a
transition time of up to 100µsec is permitted.
August 23, 1993
4
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
MIN
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
nDx to nQx
Propagation delay
nE to nQx
Output enable time
to High and Low level
Output disable time
from High and Low level
2
1
4
5
4
5
1.3
1.3
1.8
2.0
1.2
2.1
1.4
2.0
T
amb
= +25
o
C
V
CC
= +5.0V
TYP
2.8
2.9
3.5
3.5
2.9
3.8
3.7
3.6
MAX
4.1
4.1
4.9
4.9
4.1
5.3
5.0
4.6
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±0.5V
MIN
1.3
1.3
1.8
2.0
1.2
2.1
1.4
2.0
MAX
4.8
4.8
5.7
5.5
5.1
6.1
5.5
5.1
ns
ns
ns
ns
UNIT
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Setup time, High or Low
nDx to nE
Hold time, High or Low
nDx to nE
Enable pulse width
High
3
3
1
1.0
1.0
0.5
0.5
2.5
TYP
0.0
0.3
–0.2
0.0
1.0
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±0.5V
MIN
1.0
1.0
0.5
0.5
2.5
ns
ns
ns
UNIT
August 23, 1993
5
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