1M x 32 SRAM MODULE
PUMA 84S32000 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 2.1 : January 1999
Features
•
•
•
Access times of 70/85/100 ns.
High Density Package
JEDEC 84 'J' leaded plastic Surface Mount
Package.
•
•
•
Single 5.0 V±10% Power supply.
User Configurable as 8 / 16 / 32 bit wide output.
Operating Power
Low Power Standby
•
•
•
Fully Static operation.
Data Retention Capability (-L version only).
Multiple ground pins for maximum noise immunity.
(32-BIT)
(-L)
2.51 W (max)
8.25 mW (max)
Description
The PUMA 84S32000 is a 32Mbit CMOS Static RAM
organised as 1M x 32 in a JEDEC 84 pin surface mount
J-leaded PLCC, available with access times of 70, 85,
and 100ns. The output width is user configurable as 8,
16 or 32 bits using eight Chip Selects (CS1~8).
The PUMA 84S32000 offers a dramatic space saving
advantage over eight standard 512Kx8 devices. The -L
version has data retention capability and can be used in
battery backup applications.
Block Diagram
A0 - A18
WE
OE
512K x 8
SRAM
CS1
D0 - D7
CS5
512K x 8
SRAM
512K x 8
SRAM
D0 - D7
Pin Definition
NC
NC
D16
A18
A17
CS4
CS3
CS2
CS1
NC
VCC
CS8
CS7
CS6
CS5
OE
WE
A16
A15
A14
D15
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
512K x 8
SRAM
CS2
512K x 8
SRAM
CS3
D8 - D15
CS6
D8 - D15
D16 - D23
CS7
512K x 8
SRAM
D16 - D23
512K x 8
SRAM
CS4
D24 - D31
CS8
512K x 8
SRAM
D24 - D31
NC
NC
D17
D18
D19
GND
D20
D21
D22
D23
VCC
D24
D25
D26
D27
GND
D28
D29
D30
NC
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PUMA 84S32000
VIEW
FROM
ABOVE
67
66
65
64
63
62
61
60
59
58
57
56
55
54
NC
NC
D14
D13
D12
GND
D11
D10
D9
D8
VCC
D7
D6
D5
D4
GND
D3
D2
D1
NC
NC
NC
NC
D31
A6
A5
A4
A3
A2
A1
A0
VCC
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 ~ A18
D0 ~ D31
CS1 ~ 8
WE
OE
NC
V
CC
GND
Package Details
Plastic 84 J-Leaded JEDEC PLCC
A13
A12
A11
A10
A9
A8
A7
D0
NC
NC
ISSUE 2.1 : January 1999
PUMA 84S32000
- 70/85/10
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to GND
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.3V to 7.0
4.5
-55 to +125
V
W
°
C
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL (1)
T
A
T
AI
min
4.5
2.2
-0.3
0
-40
typ
5.0
-
-
-
-
max
5.5
V
CC
+0.3
0.8
70
85
Units
V
V
V
°
C
°
C
( Suffix
I
)
Notes: (1) Pulse width: -3.0V for less than 40ns.
DC Electrical Characteristics
(V
CC
=5V±10%,T
A
=-40°C to +85°C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol Test Condition
I
LI1
I
LO
V
IN
=0V to V
CC
V
I/O
=0V to V
CC
Cycle time = min 100% duty I
I/O
=0mA
CS=V
IL
V
IN
= V
IH
or V
IL
min
-8
-8
-
-
-
-
-
-
2.2
typ
-
-
-
-
-
-
-
-
-
max
8
8
456
244
138
32
2
0.4
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
Operating Supply Current
(2)
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Standby Supply Current
(TTL) I
SB
-L Version (CMOS) I
SB1
Output Voltage Low
Output Voltage High
V
OL
V
OH
As above.
As above.
CS
(1)
=V
IH
, V
IN
=V
IL
or V
IH
CS≥V
CC
-0.2V,Other inputs = 0~V
CC
I
OL
= 2.1mA,V
CC
=Min
I
OH
= -1.0mA,V
CC
=Min
Notes: (1) CS1~4 or CS5~8 inputs operate simultaneously for 32 bit mode.
Capacitance
(V
CC
=5V, T
A
=25°C, F=1Mhz)
Parameter
Input Capacitance
Address,OE,WE
Output Capacitance
8-bit mode (worst case)
Symbol
C
IN1
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
min
-
-
typ
-
-
max
64
80
Unit
pF
pF
Note: These parameters are calculated, not measured.
2
PUMA 84S32000
- 70/85/10
ISSUE 2.1 : January 1999
AC Test Conditions
Output Load
I/O Pin
166
Ω
1.76V
30pF
*Input pulse levels: 0.8V to 2.4V
*Input rise and fall times: 5 ns
*Input and Output timing reference levels: 1.5V
*V
cc
=5V±10%
*PUMA module is tested in 32 bit mode.
Operation Truth Table
Below is the truth table which applies to each individual SRAM on the module. When operating the
module care should be taken to prevent any two SRAM components which are connected to the same
data byte from driving the bus simultaneously. This will prevent bus contention occurring on the module.
Please refer to the block diagram on the front page of this datasheet.
Mode
Not Selected
Output Disable
Read
Write
CS
1
0
0
0
OE
X
1
0
X
WE
X
1
1
0
V
CC
Current
I
SB1
,I
SB2
I
CC1
I
CC1
I
CC1
I/O Pin
High Z
High Z
D
OUT
D
IN
Reference Cycle
Power Down
Read Cycle
Write Cycle
1 = V
IH
,
0 = V
IL
,
X = Don't Care
Low V
CC
Data Retention Characteristics - L version only
Parameter
V
CC
for Data Retention
Data Retention Current
Data Retention Time
Operation Recovery Time
Symbol
V
DR
I
CCDR1(1)
t
CDR
t
R
Test Condition
CS=V
CC
-0.2V
V
CC
= 3.0VA, CS > V
CC
-0.2V, V
IN
>0V
See Retention Waveform
See Retention Waveform
min
2.0
-
typ
-
-
-
-
max
-
1.5
-
-
Unit
V
mA
ns
ms
0
5
3
ISSUE 2.1 : January 1999
PUMA 84S32000
- 70/85/10
AC OPERATING CONDITIONS
Read Cycle
70
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Output Enable to Output in Low Z
Output Disable to Output in High Z
Chip Disable to Output in High Z
Chip Enable to Output in Low Z
85
max
-
70
70
35
-
-
25
25
0
10
max
-
85
85
45
-
-
25
25
0
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
OLZ
t
OHZ
t
CHZ
t
CLZ
min
70
-
-
-
10
5
0
0
10
min
85
-
-
-
10
5
0
0
10
min
100
-
-
-
15
5
0
0
10
max
-
100
100
50
-
-
30
30
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
70
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Output Active from End of Write
Data Hold from Write Time
Write to Output High Z
85
max
-
-
-
-
-
-
-
-
-
25
10
max
-
-
-
-
-
-
-
-
-
25
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
OW
t
DH
t
WHZ
min
70
60
60
0
50
0
30
3
0
0
min
85
70
70
0
60
0
35
3
0
0
min
100
80
80
0
70
0
40
3
0
0
max
-
-
-
-
-
-
-
-
-
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PUMA 84S32000
- 70/85/10
ISSUE 2.1 : January 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS1~4
8
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
AC Read Characteristics Notes
Data Valid
t
CHZ (3,4,5)
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS1~4
8
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
OW
(8)
Dout
High-Z
t
DH
Din
Data Valid
5
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
