MATRA MHS
HM 65768B
4 K
×
4 High Speed CMOS SRAM
Introduction
The HM 65768B is a high speed CMOS static RAM
organized as 4096
×
4 bits. It is manufactured using
MHS’s high performance CMOS technology.
Access times as fast as 25 ns are available with maximum
power consumption of only 385 mW.
The HM 65768B features fully static operation requiring
no external clocks or timing strobes. The automatic
power-down feature reduces the power consumption by
77 % when the circuit is deselected.
Each memory expansion is provided by an active low chip
select (CS) and three state drivers.
All inputs and outputs of the HM 65768 are TTL
compatible and operate from single 5 V supply thus
simplifying system design.
The HM 65768B is 100 % processed following the test
methods of MIL STD 883 and/or ESA/SCC 9000, making
it ideally suitable for military/space applications that
demand superior levels of performance and reliability.
Features
D
Fast access time
Commercial : 25/35/45/55 ns (max)
Military : 25/35/45/55 ns (max)
D
Low power consumption
Active : 200 mW (typ)
Standby : 35 mW (typ)
D
Wide temperature range :
–55°C to + 125°C
D
D
D
D
300 mils width package
TTL compatible inputs and outputs
Asynchronous
Capable of withstanding greater than 2000 V electrostatic
discharge
D
Single 5 volt supply
Interface
Block Diagram
Rev. C (16/12/94)
1
HM 65768B
Pin Configuration
Plastic 300 mils, 20 pins, DIL
Ceramic 300 mils, 20 pins, DIL
SOIC 300 mils, 20 pins, DIL
SOJ 300 mils, 20 pins.
MATRA MHS
Pinout DIL 20 pins (top view)
Logic Symbol
Pin Names
A0–A11 : Address inputs
I/O0-I/O3
Vcc
Gnd
: Input/Output
: Power
: Ground
CS
W
: Chip Select
: Write enable
Truth Table
CS
H
L
L
W
X
H
L
DATA–IN
Z
Z
Valid
DATA–OUT
Z
Valid
Z
MODE
Deselect
Read
Write
L = Low – H = High – X = H or L, Z = High impedance.
2
Rev. C (16/12/94)
MATRA MHS
HM 65768B
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . –0.5 V to +7.0 V
DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . –3.0 V to +7.0 V
DC output voltage in high Z state : . . . . . . . . . . . . . . –0.5 V to +7.0 V
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . > 2000 V
(MIL STD 883C METHOD 3015-2)
Operating Range
OPERATING VOLTAGE
Military
Commercial
(– 2)
(– 5)
5 V
±
10 %
5 V
±
10 %
OPERATING TEMPERATURE
– 55_C to + 125_C
0_C to + 70_C
Recommended DC Operating Conditions
PARAMETER
Vcc
Gnd
VIL
VIH
DESCRIPTION
Supply Voltage
Ground
Input low voltage
Input high voltage
MINIMUM
4.5
0.0
– 0.5
2.2
TYPICAL
5.0
0.0
0.0
–
MAXIMUM
5.5
0.0
0.8
5.5
UNIT
V
V
V
V
Capacitance
PARAMETER
Cin
Cout
Note :
(1)
(1)
DESCRIPTION
Input capacitance
Output capacitance
MINIMUM
–
–
TYPICAL
–
–
MAXIMUM
4
7
UNIT
pF
pF
1. TA = 25°C, f = 1 MHz, Vcc = 5.0 V.
DC Parameters
PARAMETER
IIX
IOZ
IOS
VOL
VOH
Note :
(3)
(3)
(4)
(5)
(2)
DESCRIPTION
Input leakage current
Output leakage current
Output short circuit current
Output low voltage
Output high voltage
MINIMUM
– 10.0
– 10.0
–
–
2.4
TYPICAL
–
–
–
–
–
MAXIMUM
10.0
10.0
– 350.0
0.4
–
UNIT
µA
µA
mA
V
V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds.
Not more than 1 output should be shorted at one time.
4. Vcc min, IOL = 8.0 mA.
5. Vcc min, IOH = –4.0 mA.
Rev. C (16/12/94)
3
HM 65768B
Consumption for Commercial (–5) Specification
SYMBOL
ICCSB
ICCOP
(6)
(7)
MATRA MHS
PARAMETER
Standby supply current
Dynamic operating current
65768B H–5 65768B K–5 65768B M–5 65768B N–5
15
70
15
70
15
70
30
90
UNIT
mA
mA
VALUE
max
max
Consumption for Military (–2) Specification
SYMBOL
ICCSB
ICCOP
Note :
(6)
(7)
PARAMETER
Standby supply current
Dynamic operating current
65768B
H–2
30
80
65768B
K–2
20
70
65768B
M–2
20
70
65768B
N–2
20
90
UNIT
mA
mA
VALUE
max
max
6. CS
≥
VIH, a pull-up resistor to Vcc on the CS input is required to keep the device deselected during Vcc power-up otherwise
ICCSB will exceed values above.
7. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd.
AC Parameters
AC Conditions
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output loading IOL/IOH
(see figure 1a)
: . . . . . . . . . . . . . . . . . +30 pF
AC Test Loads and Waveforms
Figure 1
a
Figure 1 b
Figure 2
4
Rev. C (16/12/94)
MATRA MHS
Write Cycle : Commercial (–5) Specification
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ(9)
TWLWH
TWHAX
TWHDX
TWHQX
TEHAX
(8)
(8)
HM 65768B
PARAMETER
Write Cycle time
Address set–up time
Address valid to end of write
Data set–up time
CS low to write end
Write low to high Z
Write pulse width
Address hold from end of write
Data hold time
Write high to low Z
Address hold from end CS
65768B H–5 65768B K–5
25
0
20
15
25
10
20
2
0
0
3
35
0
30
15
35
15
30
2
3
0
3
65768B
M/N–5
40
0
35
15
35
20
35
2
3
0
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
max
min
min
min
min
min
Write Cycle : Military (–2) Specification
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ(9)
TWLWH
TWHAX
TWHDX
TWHQX
TEHAX
Notes :
(8)
(8)
PARAMETER
Write Cycle time
Address set–up time
Address valid to end of write
Data set–up time
CS low to write end
Write low to high Z
Write pulse width
Address hold from end of write
Data hold time
Write high to low Z
Address hold from end CS
65768B
H–2
25
0
20
15
25
10
20
2
0
3
3
65768B
K–2
35
0
30
15
35
15
30
2
0
6
3
65768B
M–2
40
0
35
15
35
20
35
2
3
6
3
65768B
N–2
40
0
35
15
35
20
35
2
3
6
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
max
min
min
min
min
min
8. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. TWLQZ and TEHQZ are specified with CL = 5 pF as in part (1b) of AC test loads.
Rev. C (16/12/94)
5
FPGA/CPLD
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