Preliminary Data Sheet
MU9C1965A/L LANCAM
®
MP
APPLICATION BENEFITS
The 128 bit x 1024 LANCAM MP facilitates numerous
operations:
Ø
Simplified switching/routing address
filtering and translation
DISTINCTIVE CHARACTERISTICS
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1024 x 128-bit CMOS content-addressable
memory (CAM)
32-bit I/O
Fast 50 ns compare speed
Dual configuration register set for rapid context
switching
32-bit CAM/RAM segments with MUSIC’s
patented partitioning
/MA and /MM output flags enable faster system
performance
Readable Device ID
Selectable faster operating mode with no wait
states after a no-match
Validity bit setting accessible from the Status
register
Single cycle reset for Segment Control register
80-pin TQFP package
5 volt (1965A) or 3.3 volt (1965L) operation
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Improved VLAN mapping:
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DA, SA, Port ID to VLAN ID
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Filter on any field
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IP to MAC, MAC to IP filters and translation
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DA, SA to ATM VC
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Shiftable comparand and Mask Register 2
assists proximate matching algorithms
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(3 2 )
MUX
DATA (1 2 8 )
DQ3 1 -0
(3 2 )
I/ O B U FF E R S
(3 2 )
DEMU X
DATA (1 2 8 )
(3 2 )
S O URCE AND
DE STINA TIO N
S E G M ENT
CO UNTE R S
COM PA RA ND
MAS K REGIST ER 1
MAS K REGIST ER 2
CO M M AN DS
& S T A T US
/W
/E
/CM
/EC
/R ESET
CO NT RO L
LO GI C
1 K X 2 VAL IDI TY BIT S
AD DR E SS D E CO D ER
PR IO RI T Y EN C OD ER
/M A
/M M
2
CO NT RO L
AND ST AT US
REGIS T ER S
CAM A RR AY
1 K W ORDS
X 1 2 8 BI TS
10
12
FL A G
LO GI C
/FF
/FI
/M F
/M I
Block Diagram
LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors.
MUSIC is a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.
1 October 1998 Rev. 1a
MU9C1965A/L LANCAM
®
MP
GENERAL DESCRIPTION
The MU9C1965A and MU9C1965L LANCAM
®
MPs are
1024 x 128-bit content-addressable memories (CAMs),
featuring a 32-bit wide interface. The wide comparand width
allows the LANCAM MP to handle multiple protocols in a
single search table device.
Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In a RAM, the input to the device is an
address and the output is the data stored at that address.
In a CAM, the input is a data sample and the output is a
flag to indicate a match and the address of the matching
data. As a result, a CAM searches large databases for
matching data in a short, constant time period, no matter
how many entries are in the database. The ability to search
data words up to 128 bits wide allows large address spaces
to be searched rapidly and efficiently. A patented
architecture links each CAM entry to associated data and
makes this data available for use after a successful compare
operation.
The MUSIC LANCAM MP is ideal for address filtering and
translation applications in LAN and ATM switches and
routers that need the wide Comparand for Virtual LANs, VC
translation, or IPV6 address recognition. The 128-bit CAM
width is enough to include the DA, SA, Port ID, and Virtual
LAN ID for LAN switches, or DA, SA, and VC for ATM
switches. The LANCAM MP is also well suited for
encryption, database accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the LANCAM MP, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether
or not one or more of the valid CAM locations contains
data that matches the target data. The status of each CAM
location is determined by two validity bits at each memory
location. The two bits are encoded to render four validity
conditions: Valid, Skip, Empty, and Random access, as
shown in Table 1. The memory can be partitioned into CAM
and associated RAM segments on 32-bit boundaries, but
by using one of the two available mask registers, the CAM/
RAM partitioning can be set at any arbitrary size between
zero and 128 bits.
The LANCAM MP’s internal data path is 128 bits wide for
rapid internal comparison and data movement. Vertical
Skip Bit
0
0
1
1
Empty Bit
0
1
0
1
Entry Type
Valid
Empty
Skip
RAM
cascading of additional LANCAM MPs in a daisy chain
fashion extends the CAM memory depth for large
databases. Cascading requires no external logic. Loading
data to the Control, Comparand, and mask registers
automatically triggers a compare. Compares may also be
initiated by a command to the device. Associated RAM
data is available immediately after a successful compare
operation. The Status register reports the results of
compares including all flags and addresses. Two mask
registers are available and can be used in two different
ways: to mask comparisons or to mask data writes. The
random access validity type allows additional masks to be
stored in the CAM array where they may be retrieved
rapidly.
A simple four-wire control interface and commands loaded
into the Instruction decoder control the device. A powerful
instruction set increases the control flexibility and minimizes
software overhead. Additionally, dedicated pins for match
and multiple match flags enhance performance when the
device is controlled by a state machine. These and other
features make the LANCAM MP a powerful associative
memory that drastically reduces search delays.
Table 1: Entry Types vs. Validity Bits
Rev. 1a
2
MU9C1965A/L LANCAM
®
MP
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout
and bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL)
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, /EC. The rising
edge locks the daisy chain, turns off the DQ pins, and clocks
the Destination and Source Segment counters. The four
cycle types enabled by /E are shown in Table 2.
DQ31–0 (Data Bus, I/O, TTL)
The DQ31–0 lines convey data, commands, and status to
and from the LANCAM MP, as shown in Table 3. /W and
/CM control the direction and nature of the information
that flows to or from the device. When /E is HIGH,
DQ31–0 go to Hi-Z.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid matches
occur during a Compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on
the first cycle that /EC is registered LOW by the previous
falling edge of /E; see Figure 5 on page 15). In a daisy
chain, valid match(es) in higher priority devices are passed
from the /MI input to /MF. If the daisy chain is enabled but
the match flag is disabled in the Control register, the /MF
output only depends on the /MI input of the device (/MF=
/MI). /MF is HIGH if there is no match or when the daisy
chain is disabled (/E goes HIGH when /EC was HIGH on the
previous falling edge of /E). The System Match flag is the
/MF pin of the last device in the daisy chain. /MF will be
reset when the active configuration register set is changed.
/W
LOW
LOW
HIGH
HIGH
/CM
Cycle Type
LOW
Command Write Cycle
HIGH
Data Write Cycle
LOW
Command Read Cycle
HIGH
Data Read Cycle
Table 2: I/O Cycles
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ31–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input
enables the /MF output to show the results of a comparison,
as shown in Figure 5 on page 15. If /EC is LOW at the
falling edge of /E in a given cycle, the /MF output is enabled.
Otherwise, the /MF output is held HIGH. The /EC signal
also enables the /MF–/MI daisy chain, which serves to
select the device with the Highest-Priority Match in a string
of LANCAMs. Tables 6a and 6b on page 12 explain the
effect of the /EC signal on a device with or without a match
in both Standard and Enhanced modes. /EC must be HIGH
during initialization.
GND
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND
GND
42
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
41
GND
VCC
VCC
/C M
/ MA
/ EC
/ FI
G ND
G ND
DQ9
D Q 10
D Q 11
NC
VCC
VCC
TEST 2
NC
G ND
G ND
D Q 12
D Q 13
G ND
G ND
D Q 14
D Q 15
D Q 16
NC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
NC
/ FF
/ MI
/ MF
/ MM
GND
GND
/ R ESE T
VCC
VCC
/E
/W
VCC
VCC
TEST 1
NC
D Q 31
D Q 30
GND
GND
80-Pin TQFP
(Top View)
31
30
29
28
27
26
25
24
23
22
21
10
11
12
13
14
15
16
17
18
D Q 28
19
D Q 29
D Q 17
D Q 18
D Q 19
D Q 20
VCC
D Q 21
D Q 22
D Q 23
D Q 24
D Q 25
D Q 26
D Q 27
GND
GND
GND
GND
GND
Pinout Diagram
3
GND
20
1
2
3
4
5
6
7
8
9
Rev. 1a
MU9C1965A/L LANCAM
®
MP
PIN DESCRIPTIONS
Continued
/MI (Match Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in
the chain must be tied HIGH.
/MA (Device Match Flag, Output, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare cycle.
The /MA output is not qualified by /EC or /MI, and reflects
the match flag from that specific device’s Status register.
/MA will be reset when the active register set is changed.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare cycle.
The /MM output is not qualified by /EC or /MI, and reflects
the Multiple Match flag from that specific device’s Status
register. /MM will be reset when the active register set is
changed.
/FF (Full Flag, Output, TTL)
If enabled in the Control register, the /FF output goes LOW
when no empty memory locations exist within the device
(and in the daisy chain above the device as indicated by
the /FI pin). The System Full flag is the /FF pin of the last
device in the daisy chain, and the Next Free address resides
in the device with /FI LOW and /FF HIGH. If disabled in the
Control register, the /FF output only depends on the /FI
input (/FF = /FI).
/FI (Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected
to the /FF output of the previous device in the daisy chain.
The /FI pin on the first device in a chain must be tied LOW.
/RESET (Reset, Input, TTL)
/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 5 on page 10. The /RESET pin
should be driven by TTL levels, not directly by an RC
timeout. /E must be kept HIGH during /RESET.
TEST1, TEST2 (Test, Input, TTL)
These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of this product.
VCC, GND (Positive Power Supply, Ground)
These pins are the power supply connections to the
LANCAM MP. VCC must meet the voltage supply
requirements in the Operating Conditions section relative
to the GND pins, which are at 0 Volts (system reference
potential), for correct operation of the device. All the
ground and power pins must be connected to their
respective planes with adequate bulk and high frequency
bypassing capacitors in close proximity to the device.
Note: -90 or slower switching characteristics can be
operated without the GND connections on pins 1, 2, 20, 21,
22, 41, 42, 60, 61, and 62. MUSIC, however, recommends the
usage of these GND connections to ensure full compatibility
with future products.
/W
LOW
/CM
LOW
Cycle Type
Command write
HIGH
LOW
HIGH
Notes:
LOW
HIGH
HIGH
Command read
TCO 2nd cycle
Data write
Data read
“f” Bit
0
1
0
1
X
X
X
X
DQ31–16
Non-TCO Instruction
Non-TCO Instruction
TCO Instruction (Read register)*
TCO Instruction (Write register)
Status Register bits 31–16
Status Register bits 31–16†
Data to CR, MRX, Mem.
Data from CR, MRX, Mem.
DQ15–0
XXXX
Absolute Address
XXXX
Value to Register
Status Register bits 15–0
Register contents*
Data to CR, MRX, Mem.
Data from CR, MRX, Mem.
*
A CW of a TCO Instruction with the “f” bit set to 0 sets up a Register read in the following cycle. The
following cycle must be a Command Read cycle, otherwise the register read will be cancelled.
†
Upper 16 bits will be Status Register bits 31–16, except for a read of the Page Address register, in which
case they will be all zeros.
Table 3: DQ Bus Multiplexing
Rev. 1a
4
MU9C1965A/L LANCAM
®
MP
FUNCTIONAL DESCRIPTION
The LANCAM MP is a content-addressable memory
(CAM) with a 32-bit I/O for network address filtering and
translation, virtual memory, data compression, caching, and
table lookup applications. The memory consists of static
CAM, organized in 128-bit data fields. Each data field can
be partitioned into a CAM and a RAM subfield on 32-bit
boundaries. The contents of the memory can be randomly
accessed or associatively accessed by the use of a compare.
During automatic comparison cycles, data in the
Comparand register is automatically compared with the
“Valid” entries in the memory array. The Device ID can be
read using a TCO PS instruction (see Table 13 on page 23).
The data inputs and outputs of the LANCAM MP are
multiplexed for data and instructions over a 32-bit
I/O bus. Internally, data is handled on a 128-bit basis,
since the Comparand register, the mask registers, and
each memory entry are 128 bits wide. Memory entries
are globally configurable into CAM and RAM segments
on 32-bit boundaries, as described in US Patent 5,383,146
assigned to MUSIC Semiconductors. Seven different
CAM/RAM splits are possible, with the CAM width
going from one to four segments, and the remaining RAM
width going from three to zero segments. Finer resolution
on compare width is possible by invoking a mask register
during a compare, which does global masking on a bit
basis. The CAM subfield contains the associative data,
which enters into compares, while the RAM subfield
contains the associated data, which is not compared. In
LAN bridges, the RAM subfield can hold, for example,
port-address and aging information related to the
destination or source address information held in the
CAM subfield of a given location. In a translation
application, the CAM field can hold the dictionary
entries, while the RAM field holds the translations, with
almost instantaneous response.
Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
empty, valid, skip, or RAM. When data is written to the
active Comparand register, and the active Segment
Control register reaches its terminal count, the contents
of the Comparand register are automatically compared
with the CAM portion of all the valid entries in the
memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a
time. A Compare instruction can then be used to force
another compare between the Comparand register and
the CAM portion of memory entries of any one of the
four validity types. After a Read or Move from Memory
operation, the validity bits of the location read or moved
will be copied into the Status register, where they can be
read from the Status register using Command Read cycles.
Data can be moved from one of the data registers
(CR, MR1, or MR2) to a memory location that is based
on the results of the last comparison (Highest-Priority
Match or Next Free), or to an absolute address, or to the
location pointed to by the active Address register. Data
can also be written directly to the memory from the DQ
bus using any of the above addressing modes. The
Address register may be directly loaded and may be set
to increment or decrement, allowing DMA-type reading
or writing from memory.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background
activities. The currently active set of configuration
registers control writes, reads, moves, and compares.
The foreground set would typically be pre-loaded with
values useful for comparing input data, often called
filtering, while the background set would be pre-loaded
with values useful for housekeeping activities such as
purging old entries. Moving from the foreground task of
filtering to the background task of purging can be done
by issuing a single instruction to change the current set
of configuration registers. The match condition of the
device is reset whenever the active register set is
changed.
The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, enable or disable Match
flag, enable or disable Full flag, CAM/RAM partitioning,
disable or select masking conditions, disable or select
auto-incriminating or decrimenating the Address register,
and select Standard or Enhanced mode. The active
Segment Control register contains separate counters to
control the writing of 32-bit data segments to the selected
persistent destination, and to control the reading of
32-bit data segments from the selected persistent source.
There are two active mask registers at any one time,
which can be selected to mask comparisons or data
writes. Mask Register 1 has both a foreground and
background mode to support rapid context switching.
5
Rev. 1a
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