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LDM-ACT-40: 产品描述Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11; 产品类别逻辑逻辑; 文件大小37KB，共1页; 制造商Engineered Components Co

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LDM-ACT-40概述

Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11

LDM-ACT-40规格参数

参数名称	属性值
厂商名称	Engineered Components Co
零件包装代码	DMA
包装说明	QIP, DIP16,.3
针数	16/11
Reach Compliance Code	unknown
其他特性	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED
系列	ACT
JESD-30 代码	R-XDMA-P11
长度	22.86 mm
逻辑集成电路类型	ACTIVE DELAY LINE
功能数量	1
抽头/阶步数	5
端子数量	11
最高工作温度	85 °C
最低工作温度	-40 °C
输出极性	TRUE
封装主体材料	UNSPECIFIED
封装代码	QIP
封装等效代码	DIP16,.3
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
电源	5 V
可编程延迟线	NO
Prop。Delay @ Nom-Sup	40 ns
认证状态	Not Qualified
座面最大高度	6.096 mm
最大供电电压 (Vsup)	5.25 V
最小供电电压 (Vsup)	4.75 V
标称供电电压 (Vsup)	5 V
表面贴装	NO
技术	CMOS
温度等级	INDUSTRIAL
端子形式	PIN/PEG
端子节距	2.54 mm
端子位置	DUAL
总延迟标称（td）	40 ns
宽度	10.16 mm
Base Number Matches	1

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Advanced CMOS Logic Delay Module

The Advanced CMOS Logic Delay Modules manufactured by Engineered Components Company are designed

to provide output waveforms that reproduce the input waveform after a set amount of delay time has elapsed.

The five output waveforms are delay line taps provided at 20% increments of the total delay

(20, 40, 60, 80, and 100%). These delay modules are non-inverting. The delay times are calibrated to the

listed tolerances on the rising edge delays. The products with a total delay of less than 30ns have additional

delay present at tap 1 due to internal propagation delays (see the Product Selection Table).

The MTBF on these modules, when calculated per MIL-HDBK-217, for a 50 deg.C ground fixed environment and

with 50VDC applied, is in excess of 1.3 million hours. The temperature coefficient of delay is less than

500 ppm/deg.C over the operating temperature range of -40 to +85 deg. C.

The module is provided in a 16-pin DIP package, fully encapsulated in epoxy resin and is housed in a Diallyl

Phthalate case, blue in color. The case marking is applied by silkscreen using white epoxy paint. The 11

copper leads are tin-lead plated and meet the solderability requirements of MIL-STD-202, Method 208.

BLOCK DIAGRAM

12,13

MECHANICAL DIAGRAM

Output

Buffer

Input

Buffer

.150 TYP.

Delay Line

Output Output Output Output

Buffer Buffer Buffer Buffer

.060 TYP.

.300

.020 DIA. TYP.

.350 TYP.

.050 TYP.

4,5

.100 TYP.

.240

Product Selection Table

Part

Output Delay and Tolerances (in ns)

Number

Tap 1(20%) Tap 2 (40%) Tap 3 (60%) Tap 4 (80%) Tap 5 (100%)

LDM-ACT-10

6.0+/-1.0

7.0+/-1.0

8.0+/-1.0

9.0+/-1.0

10.0+/-1.0

LDM-ACT-14

6.0+/-1.0

8.0+/-1.0 10.0+/-1.0 12.0+/-1.0

14.0+/-1.0

LDM-ACT-18

6.0+/-1.0

9.0+/-1.0 12.0+/-1.0 15.0+/-1.0

18.0+/-1.0

LDM-ACT-22

6.0+/-1.0 10.0+/-1.0 14.0+/-1.0 18.0+/-1.0

22.0+/-1.0

LDM-ACT-26

6.0+/-1.0 11.0+/-1.0 16.0+/-1.0 21.0+/-1.0

26.0+/-1.0

LDM-ACT-30

6.0+/-1.0 12.0+/-1.0 18.0+/-1.0 24.0+/-1.0

30.0+/-1.5

LDM-ACT-35

7.0+/-1.0 14.0+/-1.0 21.0+/-1.0 28.0+/-1.5

35.0+/-1.5

LDM-ACT-40

8.0+/-1.0 16.0+/-1.0 24.0+/-1.0 32.0+/-1.5

40.0+/-2.0

LDM-ACT-45

9.0+/-1.0 18.0+/-1.0 27.0+/-1.5 36.0+/-1.5

45.0+/-2.0

LDM-ACT-50

10.0+/-1.0 20.0+/-1.0 30.0+/-1.5 40.0+/-2.0

50.0+/-2.0

LDM-ACT-55

11.0+/-1.0 22.0+/-1.0 33.0+/-1.5 44.0+/-2.0

55.0+/-2.0

LDM-ACT-60

12.0+/-1.0 24.0+/-1.0 36.0+/-1.5 48.0+/-2.0

60.0+/-2.0

LDM-ACT-65

13.0+/-1.0 26.0+/-1.5 39.0+/-1.5 52.0+/-2.0

65.0+/-2.5

LDM-ACT-70

14.0+/-1.0 28.0+/-1.5 42.0+/-2.0 56.0+/-2.0

70.0+/-2.5

LDM-ACT-75

15.0+/-1.0 30.0+/-1.5 45.0+/-2.0 60.0+/-2.0

75.0+/-2.5

LDM-ACT-80

16.0+/-1.0 32.0+/-1.5 48.0+/-2.0 64.0+/-2.5

80.0+/-3.0

LDM-ACT-85

17.0+/-1.0 34.0+/-1.5 51.0+/-2.0 68.0+/-2.5

85.0+/-3.0

LDM-ACT-90

18.0+/-1.0 36.0+/-1.5 54.0+/-2.0 72.0+/-2.5

90.0+/-3.0

LDM-ACT-95

19.0+/-1.0 38.0+/-1.5 57.0+/-2.0 76.0+/-2.5

95.0+/-3.0

LDM-ACT-100

20.0+/-1.0 40.0+/-1.5 60.0+/-2.0 80.0+/-3.0 100.0+/-3.0

LDM-ACT-125

25.0+/-1.0 50.0+/-2.0 75.0+/-2.5 100.0+/-3.0 125.0+/-4.0

LDM-ACT-150

30.0+/-1.5 60.0+/-2.0 90.0+/-3.0 120.0+/-4.0 150.0+/-5.0

LDM-ACT-175

35.0+/-1.5 70.0+/-2.5 105.0+/-4.0 140.0+/-4.5 175.0+/-5.0

LDM-ACT-200

40.0+/-1.5 80.0+/-3.0 120.0+/-4.0 160.0+/-5.0 200.0+/-6.0

LDM-ACT-225

45.0+/-2.0 90.0+/-3.0 135.0+/-4.0 180.0+/-6.0 225.0+/-7.0

LDM-ACT-250

50.0+/-2.0 100.0+/-3.0 150.0+/-5.0 200.0+/-6.0 250.0+/-8.0

Special modules can often be manufactured to provide for customer specific applications.

.400

LDM-ACT-26

1 2 C C 3 4 OUT

Operating Specifications:

All measurements made at 25 deg. C

All measurements made with Vcc = +5VDC

All measurements made with (1) ACT output load

Operating Temperature: -40 to +85 deg. C

Storage Temperature: -55 to +125 deg. C

Vcc Supply Voltage: 4.75 to 5.25VDC

Vcc Supply Current:

Constant “0” or “1” in = 1nA typical

Constant 1 MHz square wave in = 4mA typical

Logic “High” Input:

Voltage: 2.0VDC min. ; Vcc max.

Logic “Low” Input:

Voltage: 0.8 VDC max.

Logic “High” Voltage Out: 4.3VDC min. @ -24mA

Logic “Low” Voltage Out: 0.44VDC max. @ +24mA

engineered components company

A Division of Cornucopia Tool & Plastics, Inc. PO Box 1915, 448 Sherwood Rd., Paso Robles CA 93447

YYWW

.030

DATE CODE

V V

+/-.020

.165

Top view

.900

Phone: 805-369-0034

Fax:

805-369-0033

Web: www.ec2.com

LDM-ACT-40相似产品对比

	LDM-ACT-40	LDM-ACT-85	LDM-ACT-18	LDM-ACT-90	LDM-ACT-95
描述	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11
厂商名称	Engineered Components Co	Engineered Components Co	Engineered Components Co	Engineered Components Co	Engineered Components Co
零件包装代码	DMA	DMA	DMA	DMA	DMA
包装说明	QIP, DIP16,.3	QIP, DIP16,.3	QIP, DIP16,.3	QIP, DIP16,.3	QIP, DIP16,.3
针数	16/11	16/11	16/11	16/11	16/11
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
其他特性	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED	INPUT TO 1ST TAP DELAY = 6NS; INTERNAL TERMINATION; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED
系列	ACT	ACT	ACT	ACT	ACT
JESD-30 代码	R-XDMA-P11	R-XDMA-P11	R-XDMA-P11	R-XDMA-P11	R-XDMA-P11
长度	22.86 mm	22.86 mm	22.86 mm	22.86 mm	22.86 mm
逻辑集成电路类型	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE
功能数量	1	1	1	1	1
抽头/阶步数	5	5	5	5	5
端子数量	11	11	11	11	11
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	QIP	QIP	QIP	QIP	QIP
封装等效代码	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
电源	5 V	5 V	5 V	5 V	5 V
可编程延迟线	NO	NO	NO	NO	NO
Prop。Delay @ Nom-Sup	40 ns	85 ns	18 ns	90 ns	95 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	6.096 mm	6.096 mm	6.096 mm	6.096 mm	6.096 mm
最大供电电压 (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
最小供电电压 (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
端子节距	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL
总延迟标称（td）	40 ns	85 ns	18 ns	90 ns	95 ns
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm

LDM-ACT-40

LDM-ACT-40概述

LDM-ACT-40规格参数

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