Philips Semiconductors
Preliminary specification
Integrated multistandard comb filter
FEATURES
•
One chip adaptive multistandard comb filter
•
Time discrete but continuous amplitude signal
processing with analog interfaces
•
Internal delay lines, filters, clock processing and signal
switches
•
Alignment-free
•
No hanging dots or residual cross colour on vertical
transients
•
Few external components.
QUICK REFERENCE DATA
SYMBOL
V
CCA
V
DDD
V
CCO
V
CCPLL
I
CCO
I
DDD
I
CCA
I
CCPLL
V
17(p-p)
V
10(p-p)
V
1(p-p)
V
14(p-p)
V
12(p-p)
V
15(p-p)
analog supply voltage
digital supply voltage
analog supply voltage output buffer
analog supply voltage PLL
analog supply current output buffer
digital supply current
analog supply current
analog supply current PLL
CVBS and Y input signal (peak-to-peak value)
chrominance input signal (peak-to-peak value)
subcarrier input signal (peak-to-peak value)
luminance output signal (peak-to-peak value)
chrominance output signal (peak-to-peak value)
CVBS and Y output signal (peak-to-peak value)
PARAMETER
MIN.
4.75
4.75
4.75
4.75
−
−
−
−
0.7
−
100
0.6
−
0.6
5
5
5
5
70
10
35
1.5
1
0.7
200
1
0.7
1
TYP.
GENERAL DESCRIPTION
SAA4961
The SAA4961 is an adaptive alignment-free one chip
comb filter compatible with both PAL and NTSC systems
and provides high performance in Y/C separation.
MAX.
5.5
5.5
5.5
5.5
90
20
40
3.0
1.4
1
400
1.54
1.1
1.54
UNIT
V
V
V
V
mA
mA
mA
mA
V
V
mV
V
V
V
ORDERING INFORMATION
TYPE
NUMBER
SAA4961
PACKAGE
NAME
DIP28
DESCRIPTION
plastic dual in-line package; 28 leads (600 mil)
VERSION
SOT117-1
1997 Feb 03
2
Philips Semiconductors
Preliminary specification
Integrated multistandard comb filter
PINNING
SYMBOL
FSC
i.c.
BYP
i.c.
REFBP
SSYN
V
CCA
V
CCO
AGND
C
ext
OGND
C
O
FSCSW
Y
O
CVBSO
i.c.
Y
ext
/CVBS
LPFION
CSY
SYS1
DGND
V
DDD
SYS2
REFDL
COMBENA
PLLGND
V
CCPLL
i.c.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DESCRIPTION
subcarrier frequency input
internally connected
bypass mode forcing input
internally connected
decoupling capacitor for band-pass
filter reference
bypass definition input
analog supply voltage
analog supply voltage output buffer
analog ground (signal reference)
external chrominance input signal
analog ground output buffer
chrominance output signal
f
sc
reference selection input
luminance output signal
uncombed CVBS output signal
internally connected
CVBS (VBS) input signal
disable alias-filter
storage capacitor
standard select 1 input
digital ground
digital supply voltage
standard select 2 input
decoupling capacitor for delay lines
COMB-mode output signal
analog ground PLL
analog supply voltage PLL
internally connected
Fig.2 Pin configuration.
SSYN
VCCA
VCCO
AGND
6
7
SAA4961
handbook, halfpage
FSC
i.c.
BYP
i.c.
REFBP
1
2
3
4
5
28 i.c.
27 VCCPLL
26 PLLGND
25 COMBENA
24 REFDL
23 SYS2
22 VDDD
SAA4961
8
9
21 DGND
20 SYS1
19 CSY
18 LPFION
17 Yext/CVBS
16 i.c.
15 CVBSO
MHA547
Cext 10
OGND 11
CO 12
FSCSW 13
YO 14
1997 Feb 03
4
Philips Semiconductors
Preliminary specification
Integrated multistandard comb filter
FUNCTIONAL DESCRIPTION
Functional requirements
The multistandard comb filter processes the video
standards PAL B, G, H, M, N and NTSC M. PAL D and I
signals can also be processed but with the drawback of a
slightly reduced bandwidth.
For SECAM and SVHS signals the input signals can be
bypassed to the output without processing by selecting the
BYPASS-mode.
A sync separation circuit is incorporated to generate
control signals for the internal clock processing. With a
sync compression of up to 12 dB the sync separator works
properly (see Fig.4).
The IC is controlled via six pins:
1. BYP forces the IC into the BYPASS-mode (comb filter
function off)
2. SSYN defines whether the COMB-mode is entered
synchronously or not and defines the polarity of the
BYP pin
3. SYS1 selects the video standard
4. SYS2 selects the video standard
5. FSCSW selects the reference frequency f
sc
or 2
×
f
sc
6. LPFION enables the internal pre-filter.
It is possible to select the following modes of operation:
COMB-mode: luminance and chrominance comb filter
function active if BYPASS-mode not active.
BYPASS-mode: signal processing not active, all clocks
inactive, C
ext
(pin 10) is bypassed to C
O
(pin 12) and
Y
ext
/CVBS (pin 17) is bypassed to Y
O
(pin 14) and
CVBSO (pin 15). This mode is forced via BYP (pin 3).
If the stimulus of the mode is changed, the IC is following
the new mode after the stabilization time given in Table 1.
Table 1
Stabilization time after mode change
MODE CHANGE
COMB-mode to BYPASS-mode
BYPASS-mode to COMB-mode
MAXIMUM
STABILIZATION
TIME
1 line
1 field
Table 2
Bypass function
BYP
LOW
HIGH
LOW
HIGH
SSYN
LOW
LOW
HIGH
HIGH
Pin description
FSC (
PIN
1)
SAA4961
Input for the reference frequency f
sc
(see note 2 of Chapter
“Characteristics”) or 2
×
f
sc
. For SECAM standard signals
the best signal performance in BYPASS-mode is achieved
by switching the FSC input signal off externally.
BYP (
PIN
3)
Input signal that controls the operation mode. A low-pass
filter is added to the input for suppression of subcarrier
frequencies. Thus applications are supported where the
operation mode (COMB or BYPASS) is controlled by the
DC-level of the FSC input signal at pin 1. For those
applications the BYP input can be externally connected to
FSC (pin 1).
Depending on SSYN (pin 6) the function of BYP can be
adapted to a certain application with respect to the polarity
of the logic level and with respect to the behaviour when
entering the COMB-mode.
Depending on SSYN the BYP input can be either inverted
or non-inverted with the function as shown in Table 2.
SELECTED MODE
COMB-mode
BYPASS-mode
BYPASS-mode
COMB-mode
Depending on SSYN the behaviour when entering the
COMB-mode is different for the both selectable logic
polarities while the BYPASS-mode is always entered
asynchronously (immediately).
Table 3
Behaviour when entering the COMB-mode
ENTERING COMB-MODE
immediately if BYP = LOW
synchronized by vertical pulse if
BYP = HIGH
SSYN
LOW
HIGH
The mode change from BYPASS to COMB depends on
SSYN (pin 6) and can be asynchronous or synchronous
related to the vertical pulse. The mode change from
COMB to BYPASS is always performed asynchronously.
The PLL and the clock processing are always stopped if
the selected level for BYPASS is applied to BYP
(independent of the vertical pulse).
1997 Feb 03
5
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