M672061E
16 K
9 CMOS With Programmable Half Full Flag Parallel
FIFO Rad Tolerant
Description
The M672061E implements a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the TEMIC FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eight transistors (8 T) memory cell, the
M672061E combine an extremely low standby supply
current (typ = 0.1
µA)
with a fast access time at 15 ns
over the full temperature range. All versions offer battery
backup data retention capability with a typical power
consumption at less than 2
µW.
For military/space applications that demand superior
levels of performance and reliability the M672061E is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) ,ESA SCC 9000 or
QML.
Features
D
D
D
D
D
First-in first-out dual port memory
16384
×
9 organisation
Fast Flag and access times: 15, 30 ns
Wide temperature range : – 55
°C
to + 125
°C
Programmable Half Full Flag
D
D
D
D
D
D
D
D
D
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V
±
10 % power supply
High Performance SCMOS Technology
Rev. C – June 30, 1999
1
M672061E
Interface
Block Diagram
16384 x 9
16384
Pin Configuration
FP 28 pin 400 mils
(top view)
W
I
8
I
3
I
2
I
1
I
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
I
4
I
5
I
6
I
7
FL/RT
RS
EF
XO/PHF
Q
7
Q
6
Q
5
Q
4
R
2
Rev. C – June 30, 1999
M672061E
Pin Names
NAMES
I0–8
Q0–8
W
R
RS
EF
Inputs
Outputs
Write Enable
XI
Read Enable
FL/RT
Reset
VCC
Empty Flag
GND
Ground
Power Supply
First Load/Retransmit
Expansion IN
DESCRIPTION
NAMES
FF
XO/PHF
DESCRIPTION
Full Flag
Expansion Out/Programmable Half-
Full Flag
Signal Description
Data In (I
0
- I
8
)
Data inputs for 9 - bit data
the Read Enable (R) and Write Enable (W) inputs must be
in the high state during the period shown in figure 1 (i.e.
t
RSS
before the rising edge of RS) and should not change
until t
RSR
after the rising edge of RS. Otherwise, pulse
write (or read) low during the reset operation has to effect
to load the Programmable Half Full Flag register grow the
data Inputs I
0
-I
8
(or data outputs Q
0
-Q
8
) (shown in figure
2). In these two cases the Full Flag and the Programmable
Half Full Flag are reseted to high and the Empty Flag to
low.
Reset (RS)
Reset occurs whenever the Reset (RS) input is taken to a
low state. Reset returns both internal read and write
pointers to the first location. A reset is required after
power-up before a write operation can be enabled. Both
Rev. C – June 30, 1999
3
M672061E
Figure 1.
Reset (no write to Programmable Half Full Flag register)
t
WR
(t
RR)
Notes :
1. EF, FF and HF may change status during reset, but flags will be valid at t
RSC
.
2. W and R = VIH around the rising edge of RS.
Figure 2.
RS
Reset (write (read) to Programmable Half Full Flag register)
t
WR
(t
RR)
t
WPW
(
t
RPW)
t
WC
(t
RC)
t
RSR
W
(R)
t
DS
t
DH
I
0
–I
8
(Q0
–
Q8)
DATA VALID
Write Enable (W)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
Once half the memory is filled, and during the falling
edge of the next write operation, the Programmable
Half-Full Flag (PHF) will be set to low and remain in this
state until the difference between the write and read
pointers is less than or equal to half of the total available
memory in the device. The Programmable Half-Full Flag
(PHF) is then reset by the rising edge of the read
operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
stack is full, the internal write pointer is blocked from W,
so that external changes to W will have no effect on the
full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read
Enable (R) provided that the Empty Flag (EF) is not set.
The data is accessed on a first in/first out basis, not with
standing any current write operations. After Read Enable
(R) goes high, the Data Outputs (Q0 - Q8) will return to
a high impedance state until the next Read operation.
When all the data in the FIFO stack has been read, the
Empty Flag (EF) will go low, allowing the “final” read
cycle, but inhibiting further read operations whilst the
data outputs remain in a high impedance state. Once a
valid write operation has been completed, the Empty Flag
(EF) will go high after tWEF and a valid read may then
be initiated. When the FIFO stack is empty, the internal
read pointer is blocked from R, so that external changes
to R will have no effect on the empty FIFO stack.
First Load/Retransmit (FL/RT)
This is a dual-purpose input. In the Depth Expansion
Mode, this pin is connected to ground to indicate that it
4
Rev. C – June 30, 1999
M672061E
is the first loaded (see Operating Modes). In the Single
Device Mode, this pin acts as the retransmit input. The
Single Device Mode is initiated by connecting the
Expansion In (XI) to ground.
The M672061E can be made to retransmit data when the
Retransmit Enable Control (RT) input is pulsed low. A
retransmit operation will set the internal read point to the
first location and will not affect the write pointer. Read
Enable (R) and Write Enable (W) must be in the high state
during retransmit. The retransmit feature is intended for
use when a number of writes equals to or less than the
depth of the FIFO has occured since the last RS cycle. The
retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Programmable
Half-Full Flag (PHF), in accordance with the relative
locations of the read and write pointers.
operations when the read pointer is equal to the write
pointer, indicating that the device is empty.
Expansion Out/Half-Full Flag (XO/HF)
This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is connected to ground, this
output acts as an indication of a half-full memory.
The M672061E offers a variable offset for the Half Full
condition. The offset is loaded into a register during a
reset cycle . When RS is low, the Programmable Half Full
Flag (PHF) can be loaded from the DATA inputs I
0
-I
8
by
pulsing W low or from the DATA outputs Q
0
–Q
8
by
pulsing R low. The offset options are listed in table 1. If
PHF is not loaded during the reset cycle, the default offset
will be the half of the total memory of the device.
The Programmable Half-Full Flag (PHF) will be set to
low and will remain set until the difference between the
write and read pointers is less than or equal to the
Programmable offset (if the Half Full Flag register has
been loaded during the reset cycle) or the half of the total
memory (if the Half Full register has not been loaded
during the reset cycle).
In the Depth Expansion Mode, Expansion In (XI) is
connected to Expansion Out (XO) of the previous device.
This output acts as a signal to the next device in the Daisy
Chain by providing a pulse to the next device when the
previous device reaches the last memory location.
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is
connected to GND to indicate an operation in the single
device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth
Expansion or Daisy Chain modes.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write
operations when the write pointer is one location less than
the read pointer, indicating that the device is full. If the
read pointer is not moved after Reset (RS), the Full Flag
(FF) will go low after 16384 writes.
Data Output (Q
0
- Q
8
)
DATA output for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read
Rev. C – June 30, 1999
5
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
