Standard Products
ACT 5260
64-Bit Superscaler Microprocessor
www.aeroflex.com/Avionics
January 28, 2004
FEATURES
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Full militarized PMC-Sierra RM5260
microprocessor
Dual Issue superscalar PMC-Sierra RISCMark™ -
can issue one integer and one floating-point
instruction per cycle microprocessor - can issue
one integer and one floating-point instruction per
cycle
- 100, 133 and 150MHz frequency (200MHz future
option) Consult Factory for latest speeds
- 260 Dhrystone2.1 MIPS
- SPECInt95 4.8. SPECfp95 5.1
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Embedded supply de-coupling capacitors and Pll
filter components
High-performance floating point unit - up to 400
MFLOPS
- Single cycle repeat rate for common single precision
operations and some double precision operations
- Two cycle repeat rate for double precision multiply
and double precision combined multiply-add
operations
- Single cycle repeat rate for single precision
combined multiply-add operation
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High performance system interface compatible with
R4600, R4700 and R5000
- 64-bit multiplexed system address/data bus for
optimum price/performance up to 100 MHz
operating frequency
- High performance write protocols maximize
uncached write bandwidth
- Operates at input system clock multipliers of 2
through 8
- 5V tolerant I/O's
- IEEE 1149.1 JTAG boundary scan
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MIPS IV instruction set
- Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
- Conditional moves to reduce branch frequency
- Index address modes (register + register)
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Embedded application enhancements
- Specialized DSP integer Multiply-Accumulate
instruction and 3 operand multiply instruction
- I and D cache locking by set
- Optional dedicated exception vector for interrupts
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Integrated on-chip caches - up to 3.2GBps internal
data rate
- 16KB instruction - 2 way set associative
- 16KB data - 2 way set associative
- Virtually indexed, physically tagged
- Write-back and write-through on per page basis
- Pipeline restart on first double for data cache misses
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Fully static CMOS design with power down logic
- Standby reduced power mode with WAIT
instruction
- 5 Watts typical at 3.3V, less than 175 mwatts in
Standby
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Integrated memory management unit
- Fully associative joint TLB (shared by I and D
translations)
- 48 dual entries map 96 pages
- Variable page size (4KB to 16MB in 4x increments)
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208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended
to duplicate the commercial PMC-Sierra footprint
(Consult Factory)
179-pin PGA package (Future
Product)
(P10)
SCD5260 Rev B
DESCRIPTION:
The ACT5260 is a highly integrated superscalar microprocessor
that implements a superset of the MIPS IV Instruction Set
Architecture (ISA). It has a high performance 64-bit integer unit,
a high throughput, fully pipelined 64-bit floating point unit, an
operating system friendly memory management unit with a
48-entry fully associative TLB, a 16 KByte 2-way set associative
instruction cache, a 16 KByte 2-way set associative data cache,
and a high-performance 64-bit system interface. The ACT5260
can issue both an integer and a floating point instruction in the
same cycle.
The ACT5260 is ideally suited for high-end embedded control
applications such as internetworking, high performance image
manipulation, high speed printing, and 3-D visualization.
Integer Unit
Like the R5000, the ACT5260 implements the MIPS IV
Instruction Set Architecture, and is therefore fully upward
compatible with applications that run on processors
implementing the earlier generation MIPS I-III instruction sets.
Additionally, the ACT5260 includes two implementation specific
instructions not found in the baseline MIPS IV ISA but that are
useful in the embedded market place. Described in detail in the
PMC-Sierra RM5260 datasheet, these instructions are integer
multiply-accumulate and 3-operand integer multiply.
The ACT5260 integer unit includes thirty-two general purpose
64-bit registers, a load/store architecture with single cycle ALU
operations (add, sub, logical, shift) and an autonomous
multiply/divide unit. Additional register resources include: the
HI/LO result registers for the two-operand integer
multiply/divide operations, and the program counter(PC).
HARDWARE OVERVIEW
The ACT5260 offers a high-level of integration targeted at
high-performance embedded applications. Some of the key
elements of the ACT5260 are briefly described below.
Register File
The ACT5260 has thirty-two general purpose registers with
register location 0 hard wired to zero. These registers are used for
scalar integer operations and address calculation. The register file
has two read ports and one write port and is fully bypassed to
minimize operation latency in the pipeline.
Superscalar Dispatch
The ACT5260 has an efficient asymmetric superscalar dispatch
unit which allows it to issue an integer instruction and a
floating-point computation instruction simultaneously. With
respect to superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/store, while
floating-point computation instructions include floating-point
add, subtract, combined multiply-add, converts, etc. In
combination with its high throughput fully pipelined
floating-point execution unit, the superscalar capability of the
ACT5260 provides unparalleled price/performance in
computationally intensive embedded applications.
ALU
The ACT5260 ALU consists of the integer adder/subtractor, the
logic unit, and the shifter. The adder performs address
calculations in addition to arithmetic operations, the logic unit
performs all logical and zero shift data moves, and the shifter
performs shifts and store alignment operations. Each of these
units is optimized to perform all operations in a single processor
cycle
CPU Registers
Like all MIPS ISA processors, the ACT5260 CPU has a simple,
clean user visible state consisting of 32 general purpose registers,
two special purpose registers for integer multiplication and
division, a program counter, and no condition code bits.
Pipeline
For integer operations, loads, stores, and other non-floating-point
operations, the ACT5260 uses the simple 5-stage pipeline also
found in the circuits R4600, R4700, and R5000. In addition to
this standard pipeline, the ACT5260 uses an extended seven stage
pipeline for floating-point operations. Like the R5000, the
ACT5260 does virtual to physical translation in parallel with
cache access.
For additional Detail Information regarding the operation of the
PMC-Sierra [Quantum Effect Design (QED)] RISCMark™
RM5260™, 64-Bit Superscalar Microprocessor see the latest
PMC-Sierra datasheet (Revision 1.1 July 1998).
SCD5260 Rev B
3
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