74ACT377SJ: 产品描述Octal D-Type Flip-Flop with Clock Enable; 产品类别逻辑逻辑; 文件大小423KB，共13页; 制造商Fairchild; 官网地址http://www.fairchildsemi.com/; 标准

下载文档详细参数选型对比全文预览

74ACT377SJ在线购买

供应商	器件名称	价格	最低购买	库存
	74ACT377SJ	-	-	点击查看	点击购买

74ACT377SJ概述

Octal D-Type Flip-Flop with Clock Enable

74ACT377SJ规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Fairchild
零件包装代码	SOIC
包装说明	SOP, SOP20,.3
针数	20
Reach Compliance Code	compliant
其他特性	WITH HOLD MODE
系列	ACT
JESD-30 代码	R-PDSO-G20
JESD-609代码	e3
长度	12.6 mm
负载电容（CL）	50 pF
逻辑集成电路类型	D FLIP-FLOP
最大频率@ Nom-Sup	125000000 Hz
最大I（ol）	0.024 A
湿度敏感等级	1
位数	8
功能数量	1
端子数量	20
最高工作温度	85 °C
最低工作温度	-40 °C
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装等效代码	SOP20,.3
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
峰值回流温度（摄氏度）	260
电源	5 V
传播延迟（tpd）	11 ns
认证状态	Not Qualified
座面最大高度	2.1 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Matte Tin (Sn)
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
触发器类型	POSITIVE EDGE
宽度	5.3 mm
最小 fmax	125 MHz
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable

January 2008

74AC377, 74ACT377

Octal D-Type Flip-Flop with Clock Enable

Features

■

reduced by 50%

■

Ideal for addressable register applications

■

Clock enable for address and data synchronization

■

General Description

The AC/ACT377 has eight edge-triggered, D-type flip-

flops with individual D inputs and Q outputs. The com-

mon buffered Clock (CP) input loads all flip-flops simulta-

neously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock

transition, is transferred to the corresponding flip-flop's Q

output. The CE input must be stable only one setup time

prior to the LOW-to-HIGH clock transition for predictable

operation.

applications

Eight edge-triggered D-type flip-flops

Buffered common clock

Outputs source/sink 24mA

See 273 for master reset version

See 373 for transparent latch version

See 374 for 3-STATE version

ACT377 has TTL-compatible inputs

Ordering Information

Order Number

74AC377SC

74AC377SJ

74AC377MTC

74ACT377SC

74ACT377SJ

74ACT377MTC

74ACT377PC

Package

Number

M20B

M20D

MTC20

M20B

M20D

MTC20

N20A

Package Description

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

FACT™ is a trademark of Fairchild Semiconductor Corporation

74AC377, 74ACT377 Rev. 1.6.1

www.fairchildsemi.com

74ACT377SJ相似产品对比

	74ACT377SJ	74AC377_08	74AC377SC	74AC377	74ACT377	74ACT377SC	74ACT377MTC	74ACT377PC	74AC377SJ
描述	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable	Octal D-Type Flip-Flop with Clock Enable
是否Rohs认证	符合	-	符合	-	-	符合	符合	符合	符合
厂商名称	Fairchild	-	Fairchild	-	-	Fairchild	Fairchild	Fairchild	Fairchild
零件包装代码	SOIC	-	SOIC	-	-	SOIC	TSSOP	DIP	SOIC
包装说明	SOP, SOP20,.3	-	SOP, SOP20,.4	-	-	SOP, SOP20,.4	TSSOP, TSSOP20,.25	DIP, DIP20,.3	SOP, SOP20,.3
针数	20	-	20	-	-	20	20	20	20
Reach Compliance Code	compliant	-	unknow	-	-	unknown	unknown	compliant	compli
其他特性	WITH HOLD MODE	-	WITH HOLD MODE	-	-	WITH HOLD MODE	-	WITH HOLD MODE	WITH HOLD MODE
系列	ACT	-	AC	-	-	ACT	-	ACT	AC
JESD-30 代码	R-PDSO-G20	-	R-PDSO-G20	-	-	R-PDSO-G20	-	R-PDIP-T20	R-PDSO-G20
JESD-609代码	e3	-	e3	-	-	e3	-	e3	e3
长度	12.6 mm	-	12.8015 mm	-	-	12.8015 mm	-	26.075 mm	12.6 mm
负载电容（CL）	50 pF	-	50 pF	-	-	50 pF	-	50 pF	50 pF
逻辑集成电路类型	D FLIP-FLOP	-	D FLIP-FLOP	-	-	D FLIP-FLOP	-	D FLIP-FLOP	D FLIP-FLOP
最大I（ol）	0.024 A	-	0.012 A	-	-	0.024 A	-	0.024 A	0.012 A
位数	8	-	8	-	-	8	-	8	8
功能数量	1	-	1	-	-	1	-	1	1
端子数量	20	-	20	-	-	20	-	20	20
最高工作温度	85 °C	-	85 °C	-	-	85 °C	-	85 °C	85 °C
最低工作温度	-40 °C	-	-40 °C	-	-	-40 °C	-	-40 °C	-40 °C
输出极性	TRUE	-	TRUE	-	-	TRUE	-	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOP	-	SOP	-	-	SOP	-	DIP	SOP
封装等效代码	SOP20,.3	-	SOP20,.4	-	-	SOP20,.4	-	DIP20,.3	SOP20,.3
封装形状	RECTANGULAR	-	RECTANGULAR	-	-	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	-	SMALL OUTLINE	-	-	SMALL OUTLINE	-	IN-LINE	SMALL OUTLINE
峰值回流温度（摄氏度）	260	-	260	-	-	260	-	NOT APPLICABLE	260
电源	5 V	-	3.3/5 V	-	-	5 V	-	5 V	3.3/5 V
传播延迟（tpd）	11 ns	-	14.5 ns	-	-	11 ns	-	11 ns	14.5 ns
认证状态	Not Qualified	-	Not Qualified	-	-	Not Qualified	-	Not Qualified	Not Qualified
座面最大高度	2.1 mm	-	2.642 mm	-	-	2.642 mm	-	5.08 mm	2.1 mm
最大供电电压 (Vsup)	5.5 V	-	6 V	-	-	5.5 V	-	5.5 V	6 V
最小供电电压 (Vsup)	4.5 V	-	2 V	-	-	4.5 V	-	4.5 V	2 V
标称供电电压 (Vsup)	5 V	-	3.3 V	-	-	5 V	-	5 V	3.3 V
表面贴装	YES	-	YES	-	-	YES	-	NO	YES
技术	CMOS	-	CMOS	-	-	CMOS	-	CMOS	CMOS
温度等级	INDUSTRIAL	-	INDUSTRIAL	-	-	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
端子面层	Matte Tin (Sn)	-	Matte Tin (Sn)	-	-	Matte Tin (Sn)	-	Matte Tin (Sn)	Matte Tin (Sn)
端子形式	GULL WING	-	GULL WING	-	-	GULL WING	-	THROUGH-HOLE	GULL WING
端子节距	1.27 mm	-	1.27 mm	-	-	1.27 mm	-	2.54 mm	1.27 mm
端子位置	DUAL	-	DUAL	-	-	DUAL	-	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	-	NOT SPECIFIED	-	-	NOT SPECIFIED	-	NOT APPLICABLE	NOT SPECIFIED
触发器类型	POSITIVE EDGE	-	POSITIVE EDGE	-	-	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE
宽度	5.3 mm	-	7.5 mm	-	-	7.5 mm	-	7.62 mm	5.3 mm
最小 fmax	125 MHz	-	125 MHz	-	-	125 MHz	-	125 MHz	125 MHz
Base Number Matches	1	-	1	-	-	1	1	1	1