74HCU04
Hex Unbuffered Inverter
High−Performance Silicon−Gate CMOS
The 74HCU04 is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of six single−stage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a high−input impedance amplifier. For digital
applications, the HC04 is recommended.
Features
14
1
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HCU04G
AWLYWW
•
Output Drive Capability: 10 LSTTL Loads
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator
•
•
•
•
•
•
Configurations
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7.0 A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 12 FETs or 3 Equivalent Gates
These are Pb−Free Devices
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCU
04
ALYWG
G
HCU04
A
L, WL
Y
W, WW
G or
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 0
1
Publication Order Number:
74HCU04/D
74HCU04
PIN ASSIGNMENT
A1
Y1
A2
Y2
A3
Y3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
A6
Y6
A5
Y5
A4
Y4
A1
A2
A3
LOGIC DIAGRAM
1
3
5
2
4
6
Y1
Y2
Y3
A4
A5
9
11
8
10
Y4
Y5
FUNCTION TABLE
Inputs
A
L
H
Outputs
Y
H
L
A6
13
12
Y6
Y=A
PIN 14 = V
CC
PIN 7 = GND
ORDERING INFORMATION
Device
74HCU04DR2G
74HCU04DTR2G
Package
SOIC−14
(Pb−Free)
TSSOP−14*
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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74HCU04
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
260
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
– 65 to + 150
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature
Lead Temperature, 1 mm from case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
2.0
0
– 55
−
Max
6.0
V
CC
+ 125
No
Limit
Unit
V
V
_C
ns
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74HCU04
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
v
85_C
1.7
2.5
3.6
4.8
0.3
0.5
0.8
1.1
1.8
4.0
5.5
2.26
3.76
5.26
0.2
0.5
0.5
0.32
0.37
0.37
±1.0
20
Symbol
V
IH
Parameter
Test Conditions
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
6.0
6.0
– 55 to
25_C
1.7
2.5
3.6
4.8
0.3
0.5
0.8
1.1
1.8
4.0
5.5
2.36
3.86
5.36
0.2
0.5
0.5
0.32
0.32
0.32
±0.1
2.0
v
125_C
l.7
2.5
3.6
4.8
0.3
0.5
0.8
1.1
1.8
4.0
5.5
2.20
3.70
5.20
0.2
0.5
0.5
0.32
0.40
0.40
±1.0
40
mA
mA
V
Unit
V
Minimum High−Level Input
Voltage
V
out
= 0.5 V*
|I
out
|
v
20
mA
V
IL
Maximum Low−Level Input
Voltage
V
out
= V
CC
– 0.5 V*
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= GND
|I
out
|
v
20
mA
V
in
= GND
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
CC
|I
out
|
v
20
mA
V
in
= V
CC
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. For V
CC
= 2.0 V, V
out
= 0.2 V or V
CC
−
0.2 V.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
v
85_C
90
45
18
15
95
32
19
16
10
Symbol
t
PLH
,
t
PHL
Parameter
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
—
– 55 to
25_C
70
40
14
12
75
27
15
13
10
v
125_C
105
50
21
18
110
36
22
19
10
Unit
ns
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ns
C
in
Maximum Input Capacitance
pF
3. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
4. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Inverter)*
2
f
15
pF
5. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
+ I
CC
V
CC
. For load considerations, see Chapter 2 of the
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74HCU04
TYPICAL APPLICATIONS
V
CC
TEST POINT
t
r
INPUT A
90%
50%
10%
t
PHL
OUTPUT Y
t
THL
90%
50%
10%
t
TLH
*Includes all probe and jig capacitance
t
f
V
CC
GND
t
PLH
DEVICE
UNDER
TEST
OUTPUT
C
L
*
A
Y
Figure 1. Switching Waveforms
Figure 2. Test Circuit
Figure 3. Logic Detail
(1/6 of Device Shown)
R
2
R
2
> > R
1
C
1
< C
2
R
1
1/6 HCU04A 1/6 HCU04A 1/6 HCU04A
V
out
1/6 HCU04A
C
R
2
R
1
C
1
V
out
C
2
Figure 4. Crystal Oscillator
Figure 5. Stable RC Oscillator
V
CC
R
2
INPUT
1M
1 M 1/6 HCU04A
1/6 HCU04A
R
2
> 6R
1
V
out
OUTPUT
V
in
R
1
1/6 HCU04A
Figure 6. Schmitt Trigger
Figure 7. High Input Impedance Single−Stage
Amplifier with a 2 to 6 V Supply Range
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